perf arm_spe: Consolidate operation types

Consolidate operation types in a way:

(a) Extract the second-level types into separate enums.
(b) The second-level types for memory and SIMD operations are classified
    by modules. E.g., an operation may relate to general register,
    SIMD/FP, SVE, etc.
(c) The associated information tells details. E.g., an operation is
    load or store, whether it is atomic operation, etc.

Start the enum items for the second-level types from 8 to accommodate
more entries within a 32-bit integer.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
index 1259cbadfdc8098019afcd4cf65e733475310392..b555e2cc1dc36f209c23b0d84378da0ee65c1ab3 100644 (file)
--- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
@@ -36,29 +36,31 @@ enum arm_spe_op_type {
        ARM_SPE_OP_OTHER        = 1 << 0,
        ARM_SPE_OP_LDST         = 1 << 1,
        ARM_SPE_OP_BRANCH_ERET  = 1 << 2,
+};
+
+enum arm_spe_2nd_op_ldst {
+       ARM_SPE_OP_GP_REG               = 1 << 8,
+       ARM_SPE_OP_UNSPEC_REG           = 1 << 9,
+       ARM_SPE_OP_NV_SYSREG            = 1 << 10,
+       ARM_SPE_OP_SIMD_FP              = 1 << 11,
+       ARM_SPE_OP_SVE_OTHER            = 1 << 12,
+       ARM_SPE_OP_SVE_LDST             = 1 << 13,
+
+       /* Assisted information for memory / SIMD */
+       ARM_SPE_OP_LD                   = 1 << 20,
+       ARM_SPE_OP_ST                   = 1 << 21,
+       ARM_SPE_OP_ATOMIC               = 1 << 22,
+       ARM_SPE_OP_EXCL                 = 1 << 23,
+       ARM_SPE_OP_AR                   = 1 << 24,
+};
 
-       /* Second level operation type for OTHER */
-       ARM_SPE_OP_SVE_OTHER            = 1 << 16,
-
-       /* Second level operation type for LDST */
-       ARM_SPE_OP_LD                   = 1 << 16,
-       ARM_SPE_OP_ST                   = 1 << 17,
-       ARM_SPE_OP_ATOMIC               = 1 << 18,
-       ARM_SPE_OP_EXCL                 = 1 << 19,
-       ARM_SPE_OP_AR                   = 1 << 20,
-       ARM_SPE_OP_SIMD_FP              = 1 << 21,
-       ARM_SPE_OP_GP_REG               = 1 << 22,
-       ARM_SPE_OP_UNSPEC_REG           = 1 << 23,
-       ARM_SPE_OP_NV_SYSREG            = 1 << 24,
-       ARM_SPE_OP_SVE_LDST             = 1 << 25,
-
-       /* Second level operation type for BRANCH_ERET */
-       ARM_SPE_OP_BR_COND              = 1 << 16,
-       ARM_SPE_OP_BR_INDIRECT          = 1 << 17,
-       ARM_SPE_OP_BR_GCS               = 1 << 18,
-       ARM_SPE_OP_BR_CR_BL             = 1 << 19,
-       ARM_SPE_OP_BR_CR_RET            = 1 << 20,
-       ARM_SPE_OP_BR_CR_NON_BL_RET     = 1 << 21,
+enum arm_spe_2nd_op_branch {
+       ARM_SPE_OP_BR_COND              = 1 << 8,
+       ARM_SPE_OP_BR_INDIRECT          = 1 << 9,
+       ARM_SPE_OP_BR_GCS               = 1 << 10,
+       ARM_SPE_OP_BR_CR_BL             = 1 << 11,
+       ARM_SPE_OP_BR_CR_RET            = 1 << 12,
+       ARM_SPE_OP_BR_CR_NON_BL_RET     = 1 << 13,
 };
 
 enum arm_spe_common_data_source {