arm64: dts: qcom: ipq8074: Add missing MSI and 'global' IRQs

IPQ8074 has 8 MSI SPI interrupts and one 'global' interrupt.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250227-pcie-global-irq-v1-17-2b70a7819d1e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 78e1992b749573ea899e4d639eedf437cab19d59..fffb47ec244899cf45984adbe8c4f9820bef5c5f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -847,8 +847,24 @@
                        ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
                                 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
 
-                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "msi";
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &intc 0 0 142
@@ -919,8 +935,24 @@
                        ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
                                 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
 
-                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "msi";
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0",
+                                         "msi1",
+                                         "msi2",
+                                         "msi3",
+                                         "msi4",
+                                         "msi5",
+                                         "msi6",
+                                         "msi7",
+                                         "global";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &intc 0 0 75