drm/msm/a6xx: Resolve the meaning of rgb565_predicator

It's supposed to be on when the UBWC encoder version is >= 4.0.
Drop the per-GPU assignments.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660975/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 07212e3b9eac4d79289c8c370de6f165a341d1b8..05e2a079ff720347e394b70263a47f0bf950e9ff 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -611,7 +611,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
        if (IS_ERR(gpu->common_ubwc_cfg))
                return PTR_ERR(gpu->common_ubwc_cfg);
 
-       gpu->ubwc_config.rgb565_predicator = 0;
        gpu->ubwc_config.min_acc_len = 0;
        gpu->ubwc_config.ubwc_swizzle = 0x6;
        gpu->ubwc_config.macrotile_mode = 0;
@@ -638,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 
        if (adreno_is_a623(gpu)) {
                gpu->ubwc_config.highest_bank_bit = 16;
-               gpu->ubwc_config.rgb565_predicator = 1;
                gpu->ubwc_config.macrotile_mode = 1;
        }
 
@@ -652,13 +650,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
            adreno_is_a740_family(gpu)) {
                /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
                gpu->ubwc_config.highest_bank_bit = 16;
-               gpu->ubwc_config.rgb565_predicator = 1;
                gpu->ubwc_config.macrotile_mode = 1;
        }
 
        if (adreno_is_a663(gpu)) {
                gpu->ubwc_config.highest_bank_bit = 13;
-               gpu->ubwc_config.rgb565_predicator = 1;
                gpu->ubwc_config.macrotile_mode = 1;
                gpu->ubwc_config.ubwc_swizzle = 0x4;
        }
@@ -687,6 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
         */
        BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
        u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+       bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
        u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
        bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
        bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
@@ -699,7 +696,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
 
        gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
                  level2_swizzling_dis << 12 |
-                 adreno_gpu->ubwc_config.rgb565_predicator << 11 |
+                 rgb565_predicator << 11 |
                  hbb_hi << 10 | amsbc << 4 |
                  adreno_gpu->ubwc_config.min_acc_len << 3 |
                  hbb_lo << 1 | ubwc_mode);