extern int amdgpu_wbrf;
extern int amdgpu_user_queue;
+extern int amdgpu_ptl;
extern uint amdgpu_hdmi_hpd_debounce_delay_ms;
int amdgpu_rebar = -1; /* auto */
int amdgpu_user_queue = -1;
uint amdgpu_hdmi_hpd_debounce_delay_ms;
+int amdgpu_ptl = -1; /* auto */
DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
"DRM_UT_CORE",
MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)");
module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644);
+/**
+ * DOC: ptl (int)
+ * Enable PTL feature at boot time. Possible values:
+ *
+ * - -1 = auto (ASIC specific default)
+ * - 0 = disable PTL (default)
+ * - 1 = enable PTL
+ * - 2 = permanently disable PTL (cannot be re-enabled at runtime)
+ */
+MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)");
+module_param_named(ptl, amdgpu_ptl, int, 0444);
+
/* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers
*/
psp = &adev->psp;
ptl = &psp->ptl;
+ if (ptl->permanently_disabled && *ptl_state == 1)
+ return 0;
+
if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) ||
psp->sos.fw_version < 0x0036081a)
return -EOPNOTSUPP;
return -EINVAL;
}
+ /* Block enable when permanently disabled */
+ if (ptl->permanently_disabled) {
+ mutex_unlock(&ptl->mutex);
+ return -EPERM;
+ }
+
fmt1 = ptl->fmt1;
fmt2 = ptl->fmt2;
ptl_state = enable ? 1 : 0;
struct amdgpu_device *adev = drm_to_adev(ddev);
struct amdgpu_ptl *ptl = &adev->psp.ptl;
+ if (ptl->permanently_disabled)
+ return sysfs_emit(buf, "permanently disabled\n");
+
return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled");
}
return 0;
}
+static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev)
+{
+ struct amdgpu_ptl *ptl = &adev->psp.ptl;
+ bool enable;
+
+ switch (amdgpu_ptl) {
+ case 1:
+ enable = true;
+ break;
+ case 2:
+ /* Permanently disabled - cannot be re-enabled */
+ enable = false;
+ ptl->permanently_disabled = true;
+ break;
+ case -1:
+ case 0:
+ default:
+ enable = false;
+ break;
+ }
+
+ gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0);
+
+ return 0;
+}
+
static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
adev->gfx.ras->enable_watchdog_timer)
adev->gfx.ras->enable_watchdog_timer(adev);
- gfx_v9_4_3_perf_monitor_ptl_init(adev, true);
+ gfx_v9_4_3_ptl_hw_init(adev);
return 0;
}
enum amdgpu_ptl_fmt fmt2;
bool enabled;
bool hw_supported;
+ bool permanently_disabled;
/* PTL disable reference counting */
atomic_t disable_ref;
struct mutex mutex;