arm64: dts: renesas: r9a08g045: Add OPP table

Add OPP table for the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250128145616.2691841-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index d1e228b439dfd0958ccbd8c1b7b8ba3577e6758a..0364f89776e6bd09600d3b4b228036be843a4707 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -28,6 +28,33 @@
                clock-frequency = <0>;
        };
 
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-137500000 {
+                       opp-hz = /bits/ 64 <137500000>;
+                       opp-microvolt = <940000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-275000000 {
+                       opp-hz = /bits/ 64 <275000000>;
+                       opp-microvolt = <940000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-550000000 {
+                       opp-hz = /bits/ 64 <550000000>;
+                       opp-microvolt = <940000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1100000000 {
+                       opp-hz = /bits/ 64 <1100000000>;
+                       opp-microvolt = <940000>;
+                       clock-latency-ns = <300000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -40,6 +67,7 @@
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                L3_CA55: cache-controller-0 {