drm/amdgu: get RAS retire flip bits for new type of HBM

Get RAS retire flip bits for HBM with different types in various NPS modes.
Also set flip row bit and MCA R13 bit in PA in different NPS modes.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 05e3b34927c4e9ad8161145d998e20ed0c85e572..410ba014ed929fcfe5651bf01d605ae28166f9ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -188,24 +188,39 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev)
        flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;
        flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;
        flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;
+       flip_bits->flip_row_bit = 13;
        flip_bits->bit_num = 4;
+       flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;
+
+       if (nps == AMDGPU_NPS2_PARTITION_MODE) {
+               flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
+               flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
+               flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
+               flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
+       } else if (nps == AMDGPU_NPS4_PARTITION_MODE) {
+               flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
+               flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
+               flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
+               flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
+       }
 
        switch (vram_type) {
        case AMDGPU_VRAM_TYPE_HBM:
                /* other nps modes are taken as nps1 */
-               if (nps == AMDGPU_NPS2_PARTITION_MODE) {
-                       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
-                       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
-                       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
+               if (nps == AMDGPU_NPS2_PARTITION_MODE)
                        flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
-               }
+               else if (nps == AMDGPU_NPS4_PARTITION_MODE)
+                       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
 
-               if (nps == AMDGPU_NPS4_PARTITION_MODE) {
-                       flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
-                       flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
-                       flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
+               break;
+       case AMDGPU_VRAM_TYPE_HBM3E:
+               flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
+               flip_bits->flip_row_bit = 12;
+
+               if (nps == AMDGPU_NPS2_PARTITION_MODE)
                        flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
-               }
+               else if (nps == AMDGPU_NPS4_PARTITION_MODE)
+                       flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;
 
                break;
        default:

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
index ccdd6cd430f8a7a3e28370cf41962644f110ece8..63b7e7254526c6034f69f297f1fbe0a1c8ab8b8e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h
@@ -62,6 +62,7 @@
 #define UMC_V12_0_PA_C4_BIT 21
 /* row bits in SOC physical address */
 #define UMC_V12_0_PA_R0_BIT 22
+#define UMC_V12_0_PA_R10_BIT 32
 #define UMC_V12_0_PA_R11_BIT 33
 #define UMC_V12_0_PA_R12_BIT 34
 #define UMC_V12_0_PA_R13_BIT 35