drm/amdkfd: Send MES packets on correct XCC on GFX 12.1

Send the Set_Shader_Debugger packet on the correct MES pipe when
partition mode is set to non-SPX mode.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index f83e1238c1b3d807e0d6866650d1d6ebd46f4e1d..cd5a0b58c7d1721ca18428025b7d6d2aa68ecdc3 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -371,8 +371,10 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
                memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
        }
 
-       return amdgpu_mes_set_shader_debugger(pdd->dev->adev, pdd->proc_ctx_gpu_addr, spi_dbg_cntl,
-                                               pdd->watch_points, flags, sq_trap_en, 0);
+       return amdgpu_mes_set_shader_debugger(pdd->dev->adev,
+                                       pdd->proc_ctx_gpu_addr, spi_dbg_cntl,
+                                       pdd->watch_points, flags, sq_trap_en,
+                                       ffs(pdd->dev->xcc_mask) - 1);
 }
 
 #define KFD_DEBUGGER_INVALID_WATCH_POINT_ID -1

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index d7d37f01f51cbf0307be1b45836629cc3d22f55e..a399770aa4114cde8a915d576d5a3c4d57658343 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -94,7 +94,8 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
        if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr &&
            down_read_trylock(&dev->adev->reset_domain->sem)) {
                amdgpu_mes_flush_shader_debugger(dev->adev,
-                                                pdd->proc_ctx_gpu_addr, 0);
+                                                pdd->proc_ctx_gpu_addr,
+                                                ffs(pdd->dev->xcc_mask) - 1);
                up_read(&dev->adev->reset_domain->sem);
        }
        pdd->already_dequeued = true;