RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFDIV and VFRDIV for the below samples.

* __riscv_vfdiv_vv_f32m1_rm
* __riscv_vfdiv_vv_f32m1_rm_m
* __riscv_vfdiv_vf_f32m1_rm
* __riscv_vfdiv_vf_f32m1_rm_m
* __riscv_vfrdiv_vf_f32m1_rm
* __riscv_vfrdiv_vf_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(binop_frm): New declaration.
	(reverse_binop_frm): Likewise.
	(BASE): Likewise.
	* config/riscv/riscv-vector-builtins-bases.h:
	(vfdiv_frm): New extern declaration.
	(vfrdiv_frm): Likewise.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfdiv_frm): New function definition.
	(vfrdiv_frm): Likewise.
	* config/riscv/vector.md: Add vfdiv to frm_mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-single-div.c: New test.
	* gcc.target/riscv/rvv/base/float-point-single-rdiv.c: New test.

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 36c9aadd19c4dffd4a9cac4e254dbefea253edf4..61a506507ec71d47f745f5450a89dfc45d758208 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -279,6 +279,7 @@ public:
    - vfadd
    - vfsub
    - vfmul
+   - vfdiv
 */
 template<rtx_code CODE>
 class binop_frm : public function_base
@@ -302,6 +303,7 @@ public:
 
 /* Implements below instructions for frm
    - vfrsub
+   - vfrdiv
 */
 template<rtx_code CODE>
 class reverse_binop_frm : public function_base
@@ -2107,7 +2109,9 @@ static CONSTEXPR const widen_binop_frm<MINUS> vfwsub_frm_obj;
 static CONSTEXPR const binop<MULT> vfmul_obj;
 static CONSTEXPR const binop_frm<MULT> vfmul_frm_obj;
 static CONSTEXPR const binop<DIV> vfdiv_obj;
+static CONSTEXPR const binop_frm<DIV> vfdiv_frm_obj;
 static CONSTEXPR const reverse_binop<DIV> vfrdiv_obj;
+static CONSTEXPR const reverse_binop_frm<DIV> vfrdiv_frm_obj;
 static CONSTEXPR const widen_binop<MULT> vfwmul_obj;
 static CONSTEXPR const vfmacc vfmacc_obj;
 static CONSTEXPR const vfnmsac vfnmsac_obj;
@@ -2339,7 +2343,9 @@ BASE (vfwsub_frm)
 BASE (vfmul)
 BASE (vfmul_frm)
 BASE (vfdiv)
+BASE (vfdiv_frm)
 BASE (vfrdiv)
+BASE (vfrdiv_frm)
 BASE (vfwmul)
 BASE (vfmacc)
 BASE (vfnmsac)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 9c12a6b4e8f4c947042556985b5922b932d172d5..f35fd3d27cfa9443dcb50dcf63cb02faec3b87b6 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -154,7 +154,9 @@ extern const function_base *const vfwsub_frm;
 extern const function_base *const vfmul;
 extern const function_base *const vfmul_frm;
 extern const function_base *const vfdiv;
+extern const function_base *const vfdiv_frm;
 extern const function_base *const vfrdiv;
+extern const function_base *const vfrdiv_frm;
 extern const function_base *const vfwmul;
 extern const function_base *const vfmacc;
 extern const function_base *const vfnmsac;

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 35a83ef239c24870c10a356234e541c6169ee7e8..e7e6c7d8ed862d788cb46162bec7a79c6101156e 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -321,6 +321,9 @@ DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops)
 DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops)
 DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops)
 DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvv_ops)
+DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds, f_vvf_ops)
 
 // 13.5. Vector Widening Floating-Point Multiply
 DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5d3e4256cd58f9b58cff02c47447343f0fcf697c..4b6c38599470854c737db174ea41d32dc9f97e18 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -866,7 +866,7 @@
 
 ;; Defines rounding mode of an floating-point operation.
 (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
-  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul")
+  (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv")
          (cond
           [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
            (const_string "rne")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c
new file mode 100644 (file)
index 0000000..cef6ab0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfdiv_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfdiv_vv_f32m1_rm (op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfdiv_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+                         size_t vl) {
+  return __riscv_vfdiv_vv_f32m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfdiv_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfdiv_vf_f32m1_rm (op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfdiv_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+                         size_t vl) {
+  return __riscv_vfdiv_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfdiv_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfdiv_vv_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfdiv_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+                      size_t vl) {
+  return __riscv_vfdiv_vv_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfdiv\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c
new file mode 100644 (file)
index 0000000..385cddf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_vfrdiv_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfrdiv_vf_f32m1_rm (op1, op2, 2, vl);
+}
+
+vfloat32m1_t
+test_vfrdiv_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+                          size_t vl) {
+  return __riscv_vfrdiv_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfrdiv_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfrdiv_vf_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfrdiv_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+                       size_t vl) {
+  return __riscv_vfrdiv_vf_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfrdiv\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */