Enable VAES support [1/5]

gcc/
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET,
	OPTION_MASK_ISA_VAES_UNSET): New.
	(ix86_handle_option): Handle -mvaes.
	* config/i386/cpuid.h: Define bit_VAES.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect -mvaes.
	* config/i386/i386-c.c (__VAES__): New.
	* config/i386/i386.c (ix86_target_string): Add -mvaes.
	(ix86_valid_target_attribute_inner_p): Ditto.
	* config/i386/i386.h (TARGET_VAES, TARGET_VAES_P): New.
	* config/i386/i386.opt: Add -mvaes.
	* doc/invoke.texi: Ditto.

From-SVN: r255571

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4ad2df1801472ef91b79df0f0dc206da85f53854..62f1c240b2ac8cc3008a4c19b344e1dba0c22367 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-12-12  Julia Koval  <julia.koval@intel.com>
+
+       * common/config/i386/i386-common.c (OPTION_MASK_ISA_VAES_SET,
+       OPTION_MASK_ISA_VAES_UNSET): New.
+       (ix86_handle_option): Handle -mvaes.
+       * config/i386/cpuid.h: Define bit_VAES.
+       * config/i386/driver-i386.c (host_detect_local_cpu): Detect -mvaes.
+       * config/i386/i386-c.c (__VAES__): New.
+       * config/i386/i386.c (ix86_target_string): Add -mvaes.
+       (ix86_valid_target_attribute_inner_p): Ditto.
+       * config/i386/i386.h (TARGET_VAES, TARGET_VAES_P): New.
+       * config/i386/i386.opt: Add -mvaes.
+       * doc/invoke.texi: Ditto.
+
 2017-12-12  Alexandre Oliva <aoliva@redhat.com>
 
        * debug.h (gcc_debug_hooks): Add inline_entry.

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index e57317803c22dbe7705ba9bfc86a5835d84897ed..575a914311f289e6fec193ec6972a0103f5cb403 100644 (file)
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -142,6 +142,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
 #define OPTION_MASK_ISA_IBT_SET OPTION_MASK_ISA_IBT
 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
+#define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
 
 /* Define a set of ISAs which aren't available when a given ISA is
    disabled.  MMX and SSE ISAs are handled separately.  */
@@ -212,6 +213,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
 #define OPTION_MASK_ISA_IBT_UNSET OPTION_MASK_ISA_IBT
 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
+#define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -539,6 +541,19 @@ ix86_handle_option (struct gcc_options *opts,
        }
       return true;
 
+    case OPT_mvaes:
+      if (value)
+       {
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
+       }
+      else
+       {
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
+       }
+      return true;
+
     case OPT_mavx5124fmaps:
       if (value)
        {

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 3c992a8b9dd71595307df911711b2c4a21423056..41369c2e3485e9039ec8c1c620a7d0e655b54687 100644 (file)
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -100,6 +100,7 @@
 #define bit_AVX512VBMI2        (1 << 6)
 #define bit_SHSTK      (1 << 7)
 #define bit_GFNI       (1 << 8)
+#define bit_VAES       (1 << 9)
 #define bit_AVX512VNNI (1 << 11)
 #define bit_AVX512VPOPCNTDQ    (1 << 14)
 #define bit_RDPID      (1 << 22)

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index a6bafb160a9b80228dc0347702e73e224dae01a0..0cc4c4e96d6a1566eeff27ab8756ce50cfcdf0ea 100644 (file)
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -417,7 +417,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
   unsigned int has_ibt = 0, has_shstk = 0;
-  unsigned int has_avx512vnni = 0;
+  unsigned int has_avx512vnni = 0, has_vaes = 0;
 
   bool arch;
 
@@ -510,6 +510,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_avx512vnni = ecx & bit_AVX512VNNI;
       has_rdpid = ecx & bit_RDPID;
       has_gfni = ecx & bit_GFNI;
+      has_vaes = ecx & bit_VAES;
 
       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
@@ -1076,6 +1077,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
       const char *ibt = has_ibt ? " -mibt" : " -mno-ibt";
       const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
+      const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
                        sse4a, cx16, sahf, movbe, aes, sha, pclmul,
                        popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
@@ -1086,7 +1088,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
                        xsavec, xsaves, avx512dq, avx512bw, avx512vl,
                        avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
                        clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk,
-                       avx512vbmi2, avx512vnni, NULL);
+                       avx512vbmi2, avx512vnni, vaes, NULL);
     }
 
 done:

diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index fc667a763129e90ce3a6eba374be87dcd7bb9144..8ccec7bc29f23e0ae4d3219a28b860f63854379c 100644 (file)
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -482,6 +482,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       if (flag_cf_protection != CF_NONE)
        def_or_undef (parse_in, "__CET__");
     }
+  if (isa_flag2 & OPTION_MASK_ISA_VAES)
+    def_or_undef (parse_in, "__VAES__");
   if (TARGET_IAMCU)
     {
       def_or_undef (parse_in, "__iamcu");

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e323102cef5960d7cf8946612157245cf5ce1862..53317cf3d0ac6d93bd62169bb4d6019e23e21de0 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2748,6 +2748,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
     { "-mmpx",         OPTION_MASK_ISA_MPX },
     { "-mavx512vbmi2", OPTION_MASK_ISA_AVX512VBMI2 },
     { "-mavx512vnni", OPTION_MASK_ISA_AVX512VNNI },
+    { "-mvaes",                OPTION_MASK_ISA_VAES },
     { "-mrdpid",       OPTION_MASK_ISA_RDPID },
     { "-msgx",         OPTION_MASK_ISA_SGX },
     { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW },
@@ -5322,6 +5323,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
     IX86_ATTR_ISA ("gfni",     OPT_mgfni),
     IX86_ATTR_ISA ("ibt",      OPT_mibt),
     IX86_ATTR_ISA ("shstk",    OPT_mshstk),
+    IX86_ATTR_ISA ("vaes",     OPT_mvaes),
 
     /* enum options */
     IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 3477aa9eba789baee24fb97cba8e4fea692bda2c..01fd6ce52bbd6cd749f5de07c6a6517b31d3cde0 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -109,6 +109,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_RDPID_P(x)      TARGET_ISA_RDPID_P(x)
 #define TARGET_GFNI    TARGET_ISA_GFNI
 #define TARGET_GFNI_P(x)       TARGET_ISA_GFNI_P(x)
+#define TARGET_VAES    TARGET_ISA_VAES
+#define TARGET_VAES_P(x)       TARGET_ISA_VAES_P(x)
 #define TARGET_BMI     TARGET_ISA_BMI
 #define TARGET_BMI_P(x)        TARGET_ISA_BMI_P(x)
 #define TARGET_BMI2    TARGET_ISA_BMI2

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 6632ba800248be98278de9786a9e396ceffb0cfa..04e391d311d032e5ea59f8f3d7c37ca151f8545c 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -785,6 +785,10 @@ mgfni
 Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save
 Support GFNI built-in functions and code generation.
 
+mvaes
+Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save
+Support VAES built-in functions and code generation.
+
 mbmi
 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
 Support BMI built-in functions and code generation.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6402a5ae1734e1c1d8f7f42ba5cdec047bee0639..0d565b48f21e03ab2cae426d4735d078c3cc7518 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1204,7 +1204,7 @@ See RS/6000 and PowerPC Options.
 -mprefetchwt1  -mclflushopt  -mxsavec  -mxsaves @gol
 -msse4a  -m3dnow  -m3dnowa  -mpopcnt  -mabm  -mbmi  -mtbm  -mfma4  -mxop @gol
 -mlzcnt  -mbmi2  -mfxsr  -mxsave  -mxsaveopt  -mrtm  -mlwp  -mmpx  @gol
--mmwaitx  -mclzero  -mpku  -mthreads -mgfni @gol
+-mmwaitx  -mclzero  -mpku  -mthreads -mgfni  -mvaes  @gol
 -mcet -mibt -mshstk -mforce-indirect-call -mavx512vbmi2 @gol
 -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
@@ -26101,10 +26101,13 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @itemx -mgfni
 @opindex mgfni
+@need 200
+@itemx -mvaes
+@opindex mvaes
 These switches enable the use of instructions in the MMX, SSE,
 SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
 SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
-AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, BMI, BMI2,
+AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, BMI, BMI2, VAES,
 FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK, AVX512VBMI2,
 GFNI, 3DNow!@: or enhanced 3DNow!@: extended instruction sets.  Each has a
 corresponding @option{-mno-} option to disable use of these instructions.