RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2...

Add asm dump check test for vec_duplicate + vand.vv combine to vand.vx,
with the GR2VR cost is 0, 2 and 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add test cases
	for vand vx combine case 0 on GR2VR cost.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for vand.vx run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 47fa654e62d96bafb0c95852bd2c85dc337a8a10..ad63a84c93500034f0b7082c7b1a1e6c38620031 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 9e16eaf5930425e33578044f3e291198aa9f5d46..87d7ecbb3febbbd98333f214f3d0e3ca5a613736 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 52271bee7710ddfa411d405cc4af34583a29c610..4a402e5fe2cd39e734b4ca6fb4e34d35075d9dc5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index ac822fb66c8c419a1d61bfa73431433a9e3f8e89..b30c539f3101967a2ab65d449ed90b864c9aa19a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index f4e46b7e973e4808e4c05d807e695a2512fab1c1..fd3d726e7bd671ba4c481f0f802b9a54da7d565b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 9b83b6616192791c6b5d562fb4a214a9bc322792..917e370cdc69e3b72e393164e90c6fc2a2525861 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index be807889d72932648b9ba41d08f5b97e063d3abf..976a1b4687c17359900faf529d795ad1a518b22e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 5928c3f3f28685d790144a6b7f27469e610bcdc5..e96df13820b2d6c8fa4f85c3ace3ce4805455ae4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -8,7 +8,9 @@
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
 DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 631f035d2e570f7b5d40cca0f7ad0b7c7e3ed13b..4912dbf415e8ebcf19eb8104900d2df026d02ef4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index bbef0a23ccc351159bf8a79063cb9c897b1a345f..1219395bf3037e5c4134c5902c1f40e15a045a93 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index f4999fe899e93b794183637b9e971cf4c370b09b..64604e228ee7c2a28da156efc64b10b589b39497 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 3ddfda0cfdbc1030d5f09b6ab21336fec18264aa..e6d5e633b7bb62aa127e057dae5fc121059d0b51 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a4e2eb8435811f97bb721dcfe99029e9829771f7..35bf020705df85e706ba3f3f959ce56685ba9dec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 87ea54d0d02385c988b5b18bde0a40609fee6a82..2c9d857dcbf27a498a96b980d49ebed3c95a4c5d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 990145ccc3c085f2322ada5284f67d0730f6898a..ac49bffba63b2e31a61e6710707c593d02dba163 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index d1495a4c486786908ae75bd08abd0f6cf31c3917..8a3d027a57e14255962a9410217ccb2be8de9b29 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 9c3102a24c04768c2bf27f4db400402f1a2b4d3e..b57d4e41b3462279b726eb480d9dd0f7db85de0c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 7da01011ce751c3f2d52a7ac4b81e4a670632383..517fc0a3ed3af0261d037616887084a8be7d246e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 7e77db986bfd534f4cc21475c47b76b56083ea0a..8ba77099f8596ce4fe42c01fc391d4a8edbb200d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 957654fa1fe7083438667eaabb4155632e0c71cb..e71127f45665d523bdf5122d82c2699028ba736d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a62334adb4d0459e907a63b4ac58e36f22e9e537..82d96e9289b4af89b2b06a24dba20206f0e8a2f4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index d7b31e2b589e3a5b63717b6a5c393805c2bad852..e19513ad18bd18c601c078d12d3f46e30fffecf3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 22f555082797f4be18dc76e371fb3b26d0481e59..62a47ec14b0017dae6f985f33009321827c3d92e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 3473c5ffc6c978ad3280cfd629091578e18c1e13..d693c367c91f6bb619bcc95bd1900bdab7a8e1b6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -7,8 +7,10 @@
 
 DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
 DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
 /* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 08d53b28ec571e61d1187700f1b8397313523c68..a5b4f95473531dfffb3df56ff730ea930da9c5b3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1182,4 +1182,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, rsub)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x0,  0x0,  0x0,  0x0,
+       0x0,  0x0,  0x0,  0x0,
+       0x1,  0x1,  0x1,  0x1,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+       0x0,  0x0,  0x0,  0x0,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+  },
+  {
+    { 0xff },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x0,    0x0,    0x0,    0x0,
+         0x0,    0x0,    0x0,    0x0,
+         0x1,    0x1,    0x1,    0x1,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+         0x0,    0x0,    0x0,    0x0,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+  },
+  {
+    { 0xffff },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x0,        0x0,        0x0,        0x0,
+             0x0,        0x0,        0x0,        0x0,
+             0x1,        0x1,        0x1,        0x1,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+             0x0,        0x0,        0x0,        0x0,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+  },
+  {
+    { 0xffffffff },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+  },
+  {
+    { 0xffffffffffffffffull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+  },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x2,  0x2,  0x2,  0x2,
+       0x0,  0x0,  0x0,  0x0,
+      0xff, 0xff, 0xff, 0xff,
+    },
+    {
+       0x1,  0x1,  0x1,  0x1,
+       0x0,  0x0,  0x0,  0x0,
+       0x0,  0x0,  0x0,  0x0,
+       0x1,  0x1,  0x1,  0x1,
+    },
+  },
+  {
+    { 0x7f },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+      0x80, 0x80, 0x80, 0x80,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+    {
+      0x7f, 0x7f, 0x7f, 0x7f,
+       0x0,  0x0,  0x0,  0x0,
+       0xf,  0xf,  0xf,  0xf,
+      0x70, 0x70, 0x70, 0x70,
+    },
+  },
+  {
+    { 0xff },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+    {
+      0xff, 0xff, 0xff, 0xff,
+      0x1f, 0x1f, 0x1f, 0x1f,
+      0x80, 0x80, 0x80, 0x80,
+       0x1,  0x1,  0x1,  0x1,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x2,    0x2,    0x2,    0x2,
+         0x0,    0x0,    0x0,    0x0,
+      0xffff, 0xffff, 0xffff, 0xffff,
+    },
+    {
+         0x1,    0x1,    0x1,    0x1,
+         0x0,    0x0,    0x0,    0x0,
+         0x0,    0x0,    0x0,    0x0,
+         0x1,    0x1,    0x1,    0x1,
+    },
+  },
+  {
+    { 0x7fff },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+    {
+      0x7fff, 0x7fff, 0x7fff, 0x7fff,
+         0x0,    0x0,    0x0,    0x0,
+         0xf,    0xf,    0xf,    0xf,
+      0x7000, 0x7000, 0x7000, 0x7000,
+    },
+  },
+  {
+    { 0xffff },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+    {
+      0xffff, 0xffff, 0xffff, 0xffff,
+        0x1f,   0x1f,   0x1f,   0x1f,
+      0x8000, 0x8000, 0x8000, 0x8000,
+         0x1,    0x1,    0x1,    0x1,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x2,        0x2,        0x2,        0x2,
+             0x0,        0x0,        0x0,        0x0,
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+    },
+    {
+             0x1,        0x1,        0x1,        0x1,
+             0x0,        0x0,        0x0,        0x0,
+             0x0,        0x0,        0x0,        0x0,
+             0x1,        0x1,        0x1,        0x1,
+    },
+  },
+  {
+    { 0x7fffffff },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+    {
+      0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+             0x0,        0x0,        0x0,        0x0,
+             0xf,        0xf,        0xf,        0xf,
+      0x70000000, 0x70000000, 0x70000000, 0x70000000,
+    },
+  },
+  {
+    { 0xffffffff },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+    {
+      0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+            0x1f,       0x1f,       0x1f,       0x1f,
+      0x80000000, 0x80000000, 0x80000000, 0x80000000,
+             0x1,        0x1,        0x1,        0x1,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] =
+{
+  {
+    { 0x1 },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x2,                   0x2,                   0x2,                   0x2,
+                        0x0,                   0x0,                   0x0,                   0x0,
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+    },
+    {
+                        0x1,                   0x1,                   0x1,                   0x1,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+  },
+  {
+    { 0x7fffffffffffffffull },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+    {
+      0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
+                        0x0,                   0x0,                   0x0,                   0x0,
+                        0xf,                   0xf,                   0xf,                   0xf,
+      0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
+    },
+  },
+  {
+    { 0xffffffffffffffffull },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+    {
+      0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
+                       0x1f,                  0x1f,                  0x1f,                  0x1f,
+      0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
+                        0x1,                   0x1,                   0x1,                   0x1,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
new file mode 100644 (file)
index 0000000..a6a7db8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
new file mode 100644 (file)
index 0000000..79b7569
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
new file mode 100644 (file)
index 0000000..a80d8d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
new file mode 100644 (file)
index 0000000..d0c6f4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
new file mode 100644 (file)
index 0000000..44bbaec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
new file mode 100644 (file)
index 0000000..d634a1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
new file mode 100644 (file)
index 0000000..10816c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
new file mode 100644 (file)
index 0000000..f275016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"