drm/amdgpu: Use correct MES pipe in non-SPX mode on GFX 12.1

On GFX 12.1, use the correct MES pipe instance for readiness before
sending MES commands on that pipe. Additionally, send the TLB requests
on the correct MES pipe in non-SPX modes.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index cd4acc6adc9e12e56e358983deac989e1d7a2b6b..a6feecd0d61207a48dc0323abf6d0e1a79922f3b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -859,7 +859,7 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,
        unsigned long flags;
        uint32_t seq;
 
-       if (adev->mes.ring[0].sched.ready) {
+       if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) {
                amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
                                              ref, mask, xcc_inst);
                return;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
index d68e5a2377b6340b9b654dce40c35239a9222acc..86c0846780935c55d98404bfdecf861946d0df3e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
@@ -317,10 +317,18 @@ static void gmc_v12_1_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                                    uint32_t vmhub, uint32_t flush_type)
 {
+       u32 inst;
+
+       if (vmhub >= AMDGPU_MMHUB0(0))
+               inst = 0;
+       else
+               inst = vmhub;
+
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
         */
-       if (((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) &&
+       if (((adev->gfx.kiq[inst].ring.sched.ready ||
+             adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) &&
            (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)))) {
                struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
                const unsigned eng = 17;
@@ -329,7 +337,7 @@ static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
                amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
-                               1 << vmid, 0);
+                               1 << vmid, inst);
                return;
        }