2006-10-26 Paul Brook <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (do_neon_ext): Enforce immediate range.
	(insns): Use I15 for vext.

	gas/testsute/
	* gas/arm/neon-cov.s: Add new vext test.
	* gas/arm/neon-cov.d: Ditto.

diff --git a/ChangeLog.csl b/ChangeLog.csl
index dc6168aa341e088e0cf509136446a01832ba97c9..b0a6369134c536a85cbb0f6b70e3ad19113078e3 100644 (file)
--- a/ChangeLog.csl
+++ b/ChangeLog.csl
@@ -1,3 +1,13 @@
+2006-10-26  Paul Brook  <paul@codesourcery.com>
+
+       gas/
+       * config/tc-arm.c (do_neon_ext): Enforce immediate range.
+       (insns): Use I15 for vext.
+
+       gas/testsute/
+       * gas/arm/neon-cov.s: Add new vext test.
+       * gas/arm/neon-cov.d: Ditto.
+
 2006-10-25  Paul Brook  <paul@codesourcery.com>
 
        gas/

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 13b29844e35161d065f33f1a075b4c7a9405b3f8..6c287e94df2f7aac024c76d2d4757e1332afe5ce 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12682,6 +12682,7 @@ do_neon_ext (void)
   struct neon_type_el et = neon_check_type (3, rs,
     N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
   unsigned imm = (inst.operands[3].imm * et.size) / 8;
+  constraint (imm >= 8 * neon_quad (rs), _("shift out of range"));
   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
   inst.instruction |= HI1 (inst.operands[0].reg) << 22;
   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
@@ -15782,8 +15783,8 @@ static const struct asm_opcode insns[] =
  nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
 
   /* Extract. Size 8.  */
- NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I7), neon_ext),
- NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I7), neon_ext),
+ NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
+ NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),
 
   /* Two registers, miscellaneous.  */
   /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */

diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d
index 31903271111af81cbb684376619542404be9d1e1..e3f02f811f14c5f3d83e822d6af95e1db90398d5 100644 (file)
--- a/gas/testsuite/gas/arm/neon-cov.d
+++ b/gas/testsuite/gas/arm/neon-cov.d
@@ -1338,6 +1338,7 @@ Disassembly of section \.text:
 0[0-9a-f]+ <[^>]+> f2b00040    vext\.8 q0, q0, q0, #0
 0[0-9a-f]+ <[^>]+> f2b00040    vext\.8 q0, q0, q0, #0
 0[0-9a-f]+ <[^>]+> f2b00000    vext\.8 d0, d0, d0, #0
+0[0-9a-f]+ <[^>]+> f2b00840    vext\.8 q0, q0, q0, #8
 0[0-9a-f]+ <[^>]+> f3b00040    vrev64\.8       q0, q0
 0[0-9a-f]+ <[^>]+> f3b00040    vrev64\.8       q0, q0
 0[0-9a-f]+ <[^>]+> f3b00000    vrev64\.8       d0, d0

diff --git a/gas/testsuite/gas/arm/neon-cov.s b/gas/testsuite/gas/arm/neon-cov.s
index 079e896c25e29b1c599056cce7d3cb6cbd3b5c7a..0ac30bd233b9ca2492ed2fc3762f3b97ba50a716 100644 (file)
--- a/gas/testsuite/gas/arm/neon-cov.s
+++ b/gas/testsuite/gas/arm/neon-cov.s
@@ -561,6 +561,7 @@
        vext.8 q0,q0,q0,0
        vextq.8 q0,q0,q0,0
        vext.8 d0,d0,d0,0
+       vext.8 q0,q0,q0,8
 
        .macro revs op opq vtype
        \op\vtype q0,q0