arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device

Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d818c22574ac148baa7e7b1c1b2cd0449c0a69be..7e37ccae0fb209716d8e89f8d4f748c4f3c56bf9 100644 (file)
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -62,6 +62,7 @@ obj-y += mailbox_s10.o
 obj-y  += misc_soc64.o
 obj-y  += mmu-arm64_s10.o
 obj-y  += reset_manager_s10.o
+obj-y  += wrap_handoff_soc64.o
 obj-y  += wrap_pll_config_soc64.o
 obj-y  += altera-sysmgr.o
 endif

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index d839f2884114a51ecb80e9f8497b4099e74f3534..763b077d8c1892766d701f8a7b2888442314b16c 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
@@ -17,9 +18,9 @@
 #define SOC64_HANDOFF_MAGIC_FPGA       0x46504741
 #define SOC64_HANDOFF_MAGIC_DELAY      0x444C4159
 #define SOC64_HANDOFF_MAGIC_CLOCK      0x434C4B53
+#define SOC64_HANDOFF_MAGIC_SDRAM      0x5344524d
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_MAGIC_PERI       0x50455249
-#define SOC64_HANDOFF_MAGIC_SDRAM      0x5344524d
 #else
 #define SOC64_HANDOFF_MAGIC_MISC       0x4D495343
 #endif
@@ -68,7 +69,7 @@
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_PERI             (SOC64_HANDOFF_BASE + 0x620)
 #define SOC64_HANDOFF_SDRAM            (SOC64_HANDOFF_BASE + 0x634)
-#define SOC64_HANDOFF_SDRAM_LEN                1
+#define SOC64_HANDOFF_SDRAM_LEN                5
 #endif
 
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)

diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 92051d19b737ad761c2da7b28f5835af05ae9f34..7105cdc490525d75dad592dfd7117f790a4791fe 100644 (file)
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -1,15 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
+#include <errno.h>
 #include <asm/arch/handoff_soc64.h>
 #include <asm/io.h>
-#include <errno.h>
 #include "log.h"
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
 enum endianness {
        LITTLE_ENDIAN = 0,
        BIG_ENDIAN,
@@ -26,7 +28,12 @@ static enum endianness check_endianness(u32 handoff)
        case SOC64_HANDOFF_MAGIC_FPGA:
        case SOC64_HANDOFF_MAGIC_DELAY:
        case SOC64_HANDOFF_MAGIC_CLOCK:
+       case SOC64_HANDOFF_MAGIC_SDRAM:
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+       case SOC64_HANDOFF_MAGIC_PERI:
+#else
        case SOC64_HANDOFF_MAGIC_MISC:
+#endif
                return BIG_ENDIAN;
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
        case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: