Enable testing of fres{.} and frsqrt{.} instructions. Fixes #275308.

Based on a patch by Maynard Johnson <maynardj@us.ibm.com>.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11857

diff --git a/none/tests/ppc32/jm-fp.stdout.exp b/none/tests/ppc32/jm-fp.stdout.exp
index 7c6109b07ec99878a73f04d75746f72e036d516c..b2394cf3702c7528fabc16ffac7f228886dc7f31 100644 (file)
--- a/none/tests/ppc32/jm-fp.stdout.exp
+++ b/none/tests/ppc32/jm-fp.stdout.exp
@@ -690,6 +690,40 @@ PPC floating point compare insns (two args):
        fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
 
 PPC floating point arith insns with one arg:
+        fres 0010000000000001 => 7ff0000000000000
+        fres 00100094e0000359 => 7ff0000000000000
+        fres 3fe0000000000001 => 4000000000000000
+        fres 3fe00094e0000359 => 3ffff00000000000
+        fres 8010000000000001 => fff0000000000000
+        fres 80100094e0000359 => fff0000000000000
+        fres bfe0000000000001 => c000000000000000
+        fres bfe00094e0000359 => bffff00000000000
+        fres 0000000000000000 => 7ff0000000000000
+        fres 8000000000000000 => fff0000000000000
+        fres 7ff0000000000000 => 0000000000000000
+        fres fff0000000000000 => 8000000000000000
+        fres 7ff7ffffffffffff => 7ffff00000000000
+        fres fff7ffffffffffff => fffff00000000000
+        fres 7ff8000000000000 => 7ff8000000000000
+        fres fff8000000000000 => fff8000000000000
+
+     frsqrte 0010000000000001 => 5fdf000000000000
+     frsqrte 00100094e0000359 => 5fdf000000000000
+     frsqrte 3fe0000000000001 => 3ff6000000000000
+     frsqrte 3fe00094e0000359 => 3ff6000000000000
+     frsqrte 8010000000000001 => 7ff8000000000000
+     frsqrte 80100094e0000359 => 7ff8000000000000
+     frsqrte bfe0000000000001 => 7ff8000000000000
+     frsqrte bfe00094e0000359 => 7ff8000000000000
+     frsqrte 0000000000000000 => 7ff0000000000000
+     frsqrte 8000000000000000 => fff0000000000000
+     frsqrte 7ff0000000000000 => 0000000000000000
+     frsqrte fff0000000000000 => 7ff8000000000000
+     frsqrte 7ff7ffffffffffff => 7fff800000000000
+     frsqrte fff7ffffffffffff => ffff800000000000
+     frsqrte 7ff8000000000000 => 7ff8000000000000
+     frsqrte fff8000000000000 => fff8000000000000
+
         frsp 0010000000000001 => 0000000000000000
         frsp 00100094e0000359 => 0000000000000000
         frsp 3fe0000000000001 => 3fe0000000000000
@@ -828,6 +862,40 @@ PPC floating point arith insns with one arg:
 
 PPC floating point arith insns
     with one arg with flags update:
+       fres. 0010000000000001 => 7ff0000000000000
+       fres. 00100094e0000359 => 7ff0000000000000
+       fres. 3fe0000000000001 => 4000000000000000
+       fres. 3fe00094e0000359 => 3ffff00000000000
+       fres. 8010000000000001 => fff0000000000000
+       fres. 80100094e0000359 => fff0000000000000
+       fres. bfe0000000000001 => c000000000000000
+       fres. bfe00094e0000359 => bffff00000000000
+       fres. 0000000000000000 => 7ff0000000000000
+       fres. 8000000000000000 => fff0000000000000
+       fres. 7ff0000000000000 => 0000000000000000
+       fres. fff0000000000000 => 8000000000000000
+       fres. 7ff7ffffffffffff => 7ffff00000000000
+       fres. fff7ffffffffffff => fffff00000000000
+       fres. 7ff8000000000000 => 7ff8000000000000
+       fres. fff8000000000000 => fff8000000000000
+
+    frsqrte. 0010000000000001 => 5fdf000000000000
+    frsqrte. 00100094e0000359 => 5fdf000000000000
+    frsqrte. 3fe0000000000001 => 3ff6000000000000
+    frsqrte. 3fe00094e0000359 => 3ff6000000000000
+    frsqrte. 8010000000000001 => 7ff8000000000000
+    frsqrte. 80100094e0000359 => 7ff8000000000000
+    frsqrte. bfe0000000000001 => 7ff8000000000000
+    frsqrte. bfe00094e0000359 => 7ff8000000000000
+    frsqrte. 0000000000000000 => 7ff0000000000000
+    frsqrte. 8000000000000000 => fff0000000000000
+    frsqrte. 7ff0000000000000 => 0000000000000000
+    frsqrte. fff0000000000000 => 7ff8000000000000
+    frsqrte. 7ff7ffffffffffff => 7fff800000000000
+    frsqrte. fff7ffffffffffff => ffff800000000000
+    frsqrte. 7ff8000000000000 => 7ff8000000000000
+    frsqrte. fff8000000000000 => fff8000000000000
+
        frsp. 0010000000000001 => 0000000000000000
        frsp. 00100094e0000359 => 0000000000000000
        frsp. 3fe0000000000001 => 3fe0000000000000
@@ -1360,4 +1428,4 @@ PPC float store insns with three register args:
        stfdux 7ff8000000000000,  112 => 7ff8000000000000,  112
        stfdux fff8000000000000,  120 => fff8000000000000,  120
 
-All done. Tested 67 different instructions
+All done. Tested 71 different instructions

diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
index f056d8e1ed30a5e8e43398e4276d528f641f31a1..3249d23ad3fb04fb5db29188958142800331dd56 100644 (file)
--- a/none/tests/ppc32/jm-insns.c
+++ b/none/tests/ppc32/jm-insns.c
@@ -1934,7 +1934,6 @@ static test_t tests_fcr_ops_two[] = {
 
 #if !defined (NO_FLOAT)
 
-#if 0   // TODO: Not yet supported
 static void test_fres (void)
 {
     __asm__ __volatile__ ("fres         17, 14");
@@ -1944,7 +1943,6 @@ static void test_frsqrte (void)
 {
     __asm__ __volatile__ ("frsqrte      17, 14");
 }
-#endif
 
 static void test_frsp (void)
 {
@@ -2004,8 +2002,8 @@ static void test_fctidz (void)
 #endif // #ifdef __powerpc64__
 
 static test_t tests_fa_ops_one[] = {
-   //    { &test_fres            , "        fres", },   // TODO: Not yet supported
-   //    { &test_frsqrte         , "     frsqrte", },   // TODO: Not yet supported
+    { &test_fres            , "        fres", },
+    { &test_frsqrte         , "     frsqrte", },
     { &test_frsp            , "        frsp", },
     { &test_fctiw           , "       fctiw", },
     { &test_fctiwz          , "      fctiwz", },
@@ -2025,7 +2023,6 @@ static test_t tests_fa_ops_one[] = {
 
 #if !defined (NO_FLOAT)
 
-#if 0   // TODO: Not yet supported
 static void test_fres_ (void)
 {
     __asm__ __volatile__ ("fres.        17, 14");
@@ -2035,7 +2032,6 @@ static void test_frsqrte_ (void)
 {
     __asm__ __volatile__ ("frsqrte.     17, 14");
 }
-#endif
 
 static void test_frsp_ (void)
 {
@@ -2090,8 +2086,8 @@ static void test_fctidz_ (void)
 #endif // #ifdef __powerpc64__
 
 static test_t tests_far_ops_one[] = {
-   //    { &test_fres_           , "       fres.", },   // TODO: Not yet supported
-    //    { &test_frsqrte_        , "    frsqrte.", },   // TODO: Not yet supported
+    { &test_fres_           , "       fres.", },
+    { &test_frsqrte_        , "    frsqrte.", },
     { &test_frsp_           , "       frsp.", },
     { &test_fctiw_          , "      fctiw.", },
     { &test_fctiwz_         , "     fctiwz.", },
@@ -5723,11 +5719,16 @@ static void test_float_one_arg (const char* name, test_func_t func,
    double res;
    uint64_t u0, ur;
    volatile uint32_t flags;
-   int i, zap_hi_32bits;
+   int i;
+   unsigned zap_hi_32bits, zap_lo_44bits, zap_lo_47bits;
 
    /* if we're testing fctiw or fctiwz, zap the hi 32bits,
       as they're undefined */
-   zap_hi_32bits = strstr(name, "fctiw") != NULL;
+   zap_hi_32bits = strstr(name, " fctiw")    != NULL  ? 1 : 0;
+   zap_lo_44bits = strstr(name, " fres")     != NULL  ? 1 : 0;
+   zap_lo_47bits = strstr(name, " frsqrte")  != NULL  ? 1 : 0;
+
+   assert(zap_hi_32bits + zap_lo_44bits + zap_lo_47bits <= 1);
 
    for (i=0; i<nb_fargs; i++) {
       u0 = *(uint64_t *)(&fargs[i]);
@@ -5741,7 +5742,11 @@ static void test_float_one_arg (const char* name, test_func_t func,
        ur = *(uint64_t *)(&res);
 
       if (zap_hi_32bits)
-         ur &= 0xFFFFFFFFULL;
+         ur &= 0x00000000FFFFFFFFULL;
+      if (zap_lo_44bits)
+         ur &= 0xFFFFF00000000000ULL;
+      if (zap_lo_47bits)
+         ur &= 0xFFFF800000000000ULL;
 
 #ifndef __powerpc64__
       printf("%s %016llx => %016llx",

diff --git a/none/tests/ppc64/jm-fp.stdout.exp b/none/tests/ppc64/jm-fp.stdout.exp
index fdb5905305f96f6785df6a57d63d3558289b9c14..adbdabf377516b47f7fe0c3bf7a9674cf19a2614 100644 (file)
--- a/none/tests/ppc64/jm-fp.stdout.exp
+++ b/none/tests/ppc64/jm-fp.stdout.exp
@@ -690,6 +690,40 @@ PPC floating point compare insns (two args):
        fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
 
 PPC floating point arith insns with one arg:
+        fres 0010000000000001 => 7ff0000000000000
+        fres 00100094e0000359 => 7ff0000000000000
+        fres 3fe0000000000001 => 4000000000000000
+        fres 3fe00094e0000359 => 3ffff00000000000
+        fres 8010000000000001 => fff0000000000000
+        fres 80100094e0000359 => fff0000000000000
+        fres bfe0000000000001 => c000000000000000
+        fres bfe00094e0000359 => bffff00000000000
+        fres 0000000000000000 => 7ff0000000000000
+        fres 8000000000000000 => fff0000000000000
+        fres 7ff0000000000000 => 0000000000000000
+        fres fff0000000000000 => 8000000000000000
+        fres 7ff7ffffffffffff => 7ffff00000000000
+        fres fff7ffffffffffff => fffff00000000000
+        fres 7ff8000000000000 => 7ff8000000000000
+        fres fff8000000000000 => fff8000000000000
+
+     frsqrte 0010000000000001 => 5fdf000000000000
+     frsqrte 00100094e0000359 => 5fdf000000000000
+     frsqrte 3fe0000000000001 => 3ff6000000000000
+     frsqrte 3fe00094e0000359 => 3ff6000000000000
+     frsqrte 8010000000000001 => 7ff8000000000000
+     frsqrte 80100094e0000359 => 7ff8000000000000
+     frsqrte bfe0000000000001 => 7ff8000000000000
+     frsqrte bfe00094e0000359 => 7ff8000000000000
+     frsqrte 0000000000000000 => 7ff0000000000000
+     frsqrte 8000000000000000 => fff0000000000000
+     frsqrte 7ff0000000000000 => 0000000000000000
+     frsqrte fff0000000000000 => 7ff8000000000000
+     frsqrte 7ff7ffffffffffff => 7fff800000000000
+     frsqrte fff7ffffffffffff => ffff800000000000
+     frsqrte 7ff8000000000000 => 7ff8000000000000
+     frsqrte fff8000000000000 => fff8000000000000
+
         frsp 0010000000000001 => 0000000000000000
         frsp 00100094e0000359 => 0000000000000000
         frsp 3fe0000000000001 => 3fe0000000000000
@@ -879,6 +913,40 @@ PPC floating point arith insns with one arg:
 
 PPC floating point arith insns
     with one arg with flags update:
+       fres. 0010000000000001 => 7ff0000000000000
+       fres. 00100094e0000359 => 7ff0000000000000
+       fres. 3fe0000000000001 => 4000000000000000
+       fres. 3fe00094e0000359 => 3ffff00000000000
+       fres. 8010000000000001 => fff0000000000000
+       fres. 80100094e0000359 => fff0000000000000
+       fres. bfe0000000000001 => c000000000000000
+       fres. bfe00094e0000359 => bffff00000000000
+       fres. 0000000000000000 => 7ff0000000000000
+       fres. 8000000000000000 => fff0000000000000
+       fres. 7ff0000000000000 => 0000000000000000
+       fres. fff0000000000000 => 8000000000000000
+       fres. 7ff7ffffffffffff => 7ffff00000000000
+       fres. fff7ffffffffffff => fffff00000000000
+       fres. 7ff8000000000000 => 7ff8000000000000
+       fres. fff8000000000000 => fff8000000000000
+
+    frsqrte. 0010000000000001 => 5fdf000000000000
+    frsqrte. 00100094e0000359 => 5fdf000000000000
+    frsqrte. 3fe0000000000001 => 3ff6000000000000
+    frsqrte. 3fe00094e0000359 => 3ff6000000000000
+    frsqrte. 8010000000000001 => 7ff8000000000000
+    frsqrte. 80100094e0000359 => 7ff8000000000000
+    frsqrte. bfe0000000000001 => 7ff8000000000000
+    frsqrte. bfe00094e0000359 => 7ff8000000000000
+    frsqrte. 0000000000000000 => 7ff0000000000000
+    frsqrte. 8000000000000000 => fff0000000000000
+    frsqrte. 7ff0000000000000 => 0000000000000000
+    frsqrte. fff0000000000000 => 7ff8000000000000
+    frsqrte. 7ff7ffffffffffff => 7fff800000000000
+    frsqrte. fff7ffffffffffff => ffff800000000000
+    frsqrte. 7ff8000000000000 => 7ff8000000000000
+    frsqrte. fff8000000000000 => fff8000000000000
+
        frsp. 0010000000000001 => 0000000000000000
        frsp. 00100094e0000359 => 0000000000000000
        frsp. 3fe0000000000001 => 3fe0000000000000
@@ -1462,4 +1530,4 @@ PPC float store insns with three register args:
        stfdux 7ff8000000000000,  112 => 7ff8000000000000,  112
        stfdux fff8000000000000,  120 => fff8000000000000,  120
 
-All done. Tested 73 different instructions
+All done. Tested 77 different instructions