RISC-V: Update tt-ascalon-d8's extension list [PR123492]

The Ascalon core implements the full RVA23 profile plus a few other optional
extensions.  However, the -mcpu=tt-ascalon-d8 option doesn't enable them all.
Add the missing extensions.

2026-01-08  Peter Bergner  <bergner@tenstorrent.com>

gcc/
	PR target/123492
	* config/riscv/riscv-cores.def (RISCV_CORE)<tt-ascalon-d8>: Add missing
	extensions via use of rva23s64 profile and adding zkr, smaia, smmpm,
	smnpm, smrnmi, smstateen, ssaia, ssstrict, svadu.

Signed-off-by: Peter Bergner <bergner@tenstorrent.com>

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 355b04466ed51af1136097ca64a77df6f618802c..6c7b87b5c6b446eb2fbdbff6c4d6b01f7203e7f0 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -148,11 +148,9 @@ RISCV_CORE("xt-c920v2",       "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
                              "xtheadsync",
                               "xt-c920v2")
 
-RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
-                             "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
-                             "zifencei_zihintntl_zihintpause_zimop_za64rs_"
-                             "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_"
-                             "zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b",
+RISCV_CORE("tt-ascalon-d8",   "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfwma_zvfh_"
+                             "zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_"
+                             "smstateen_ssaia_ssstrict_svadu",
                              "tt-ascalon-d8")
 
 RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"