[Morello] Add BICFLGS

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (parse_operands): Add A64C_IMM8.
	* testsuite/gas/aarch64/morello_insn.d: Add tests.
	* testsuite/gas/aarch64/morello_insn-c64.d: Likewise.
	* testsuite/gas/aarch64/morello_insn.s: Likewise.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add A64C_IMM8.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-opc.c (fields): Add a64c_imm8.
	(aarch64_print_operand): Add A64C_IMM8.
	* aarch64-opc.h (aarch64_field_kind): Add a64c_imm8.
	* aarch64-tbl.h (QL3_A64C_CA_CA_X): New macro.
	(aarch64_opcode_table): New instructions.
	(AARCH64_OPERANDS): Add A64C_IMM8.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 420e849f24b429f691054136aab0a9ff102efee8..b2ac69d5d881765437e61d733660df5f13ac6d90 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Add A64C_IMM8.
+       * testsuite/gas/aarch64/morello_insn.d: Add tests.
+       * testsuite/gas/aarch64/morello_insn-c64.d: Likewise.
+       * testsuite/gas/aarch64/morello_insn.s: Likewise.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * config/tc-aarch64.c (parse_operands, fix_insn): Add

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ceb2bb17d6b8e20e087bf6dc3c0aaca2a2dcfb04..acff6fcbc1931fea3c0a9c16eed84c92e1e0d607 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6685,6 +6685,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          info->imm.value = val;
          break;
 
+       case AARCH64_OPND_A64C_IMM8:
        case AARCH64_OPND_CCMP_IMM:
        case AARCH64_OPND_SIMM5:
        case AARCH64_OPND_FBITS:

diff --git a/gas/testsuite/gas/aarch64/morello_insn-c64.d b/gas/testsuite/gas/aarch64/morello_insn-c64.d
index b89e55e2ca843988dcf0781aacb1f84943288fc8..adab33ec2eb08b9fe410a2259ba1acd04392c2ba 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_insn-c64.d
+++ b/gas/testsuite/gas/aarch64/morello_insn-c64.d
@@ -57,6 +57,26 @@ Disassembly of section \.text:
 .*:    02c7fbf5        sub     c21, csp, #0x1fe, lsl #12
 .*:    02800ff5        sub     c21, csp, #0x3
 .*:    02c003f5        sub     c21, csp, #0x0, lsl #12
+.*:    c2ffe0c7        bicflgs c7, c6, #255
+.*:    c2e000c7        bicflgs c7, c6, #0
+.*:    c2ffe0c7        bicflgs c7, c6, #255
+.*:    c2e200c7        bicflgs c7, c6, #16
+.*:    c2ffe0df        bicflgs csp, c6, #255
+.*:    c2e000df        bicflgs csp, c6, #0
+.*:    c2ffe0df        bicflgs csp, c6, #255
+.*:    c2e200df        bicflgs csp, c6, #16
+.*:    c2ffe3e8        bicflgs c8, csp, #255
+.*:    c2e003e8        bicflgs c8, csp, #0
+.*:    c2ffe3e8        bicflgs c8, csp, #255
+.*:    c2e203e8        bicflgs c8, csp, #16
+.*:    c2ffe3ff        bicflgs csp, csp, #255
+.*:    c2e003ff        bicflgs csp, csp, #0
+.*:    c2ffe3ff        bicflgs csp, csp, #255
+.*:    c2e203ff        bicflgs csp, csp, #16
+.*:    c2d928c7        bicflgs c7, c6, x25
+.*:    c2d92be7        bicflgs c7, csp, x25
+.*:    c2d928df        bicflgs csp, c6, x25
+.*:    c2d92bff        bicflgs csp, csp, x25
 .*:    c2a4e131        add     c17, c9, x4, sxtx
 .*:    c2a4f131        add     c17, c9, x4, sxtx #4
 .*:    c2a4d131        add     c17, c9, w4, sxtw #4

diff --git a/gas/testsuite/gas/aarch64/morello_insn.d b/gas/testsuite/gas/aarch64/morello_insn.d
index bbfcca02764302d8cca4cf09629d1d812ffa4cbe..aff1b3de897e5ec40d6ba96b2d1db2da962bb0a2 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_insn.d
+++ b/gas/testsuite/gas/aarch64/morello_insn.d
@@ -56,6 +56,26 @@ Disassembly of section \.text:
 .*:    02c7fbf5        sub     c21, csp, #0x1fe, lsl #12
 .*:    02800ff5        sub     c21, csp, #0x3
 .*:    02c003f5        sub     c21, csp, #0x0, lsl #12
+.*:    c2ffe0c7        bicflgs c7, c6, #255
+.*:    c2e000c7        bicflgs c7, c6, #0
+.*:    c2ffe0c7        bicflgs c7, c6, #255
+.*:    c2e200c7        bicflgs c7, c6, #16
+.*:    c2ffe0df        bicflgs csp, c6, #255
+.*:    c2e000df        bicflgs csp, c6, #0
+.*:    c2ffe0df        bicflgs csp, c6, #255
+.*:    c2e200df        bicflgs csp, c6, #16
+.*:    c2ffe3e8        bicflgs c8, csp, #255
+.*:    c2e003e8        bicflgs c8, csp, #0
+.*:    c2ffe3e8        bicflgs c8, csp, #255
+.*:    c2e203e8        bicflgs c8, csp, #16
+.*:    c2ffe3ff        bicflgs csp, csp, #255
+.*:    c2e003ff        bicflgs csp, csp, #0
+.*:    c2ffe3ff        bicflgs csp, csp, #255
+.*:    c2e203ff        bicflgs csp, csp, #16
+.*:    c2d928c7        bicflgs c7, c6, x25
+.*:    c2d92be7        bicflgs c7, csp, x25
+.*:    c2d928df        bicflgs csp, c6, x25
+.*:    c2d92bff        bicflgs csp, csp, x25
 .*:    c2a4e131        add     c17, c9, x4, sxtx
 .*:    c2a4f131        add     c17, c9, x4, sxtx #4
 .*:    c2a4d131        add     c17, c9, w4, sxtw #4

diff --git a/gas/testsuite/gas/aarch64/morello_insn.s b/gas/testsuite/gas/aarch64/morello_insn.s
index 6a16c02d9d94c2dd220d991afc90eddcf25dbe11..d0af5e2af4f3e6068c794d24dc881565307d0ac7 100644 (file)
--- a/gas/testsuite/gas/aarch64/morello_insn.s
+++ b/gas/testsuite/gas/aarch64/morello_insn.s
@@ -28,6 +28,31 @@ morello_addsub_imm csp, c9
 morello_addsub_imm csp, csp
 morello_addsub_imm c21, csp
 
+       .macro morello_cspcspi8 cdsp, cnsp
+         .irp op, bicflgs
+               \op   \cdsp, \cnsp, #0xff
+               \op   \cdsp, \cnsp, #0
+               \op   \cdsp, \cnsp, #0xff
+               \op   \cdsp, \cnsp, #0x10
+         .endr
+       .endm
+morello_cspcspi8 c7, c6
+morello_cspcspi8 csp, c6
+morello_cspcspi8 c8, csp
+morello_cspcspi8 csp, csp
+
+// Three operands (dnm)
+
+       .macro morello_cspcspx cdsp, cnsp, xm
+         .irp op, bicflgs
+           \op   \cdsp, \cnsp, \xm
+         .endr
+       .endm
+morello_cspcspx c7, c6, x25
+morello_cspcspx c7, csp, x25
+morello_cspcspx csp, c6, x25
+morello_cspcspx csp, csp, x25
+
 // Four operands (dnmi)
 
        .macro morello_add_scalar cspd, cspn, rm

diff --git a/include/ChangeLog b/include/ChangeLog
index b183cdb007b83bc70055e2a89f9a6f3cae72f22b..675b28d9782d0ccf84d53219c4feb89b4dafa814 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * opcode/aarch64.h (aarch64_opnd): Add A64C_IMM8.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * opcode/aarch64 (aarch64_opnd): Add A64C_AIMM and

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c5e4bff1e212474541dd24153de7a10dc27ffe05..bd865bc6b25b3f4ebfac1be068609ac562dd53fd 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -516,6 +516,7 @@ enum aarch64_opnd
   AARCH64_OPND_Can_SP,         /* Capability register or Cap SP as source. */
   AARCH64_OPND_A64C_Rm_EXT,    /* Integer Xm extended.  */
   AARCH64_OPND_A64C_AIMM,      /* Add immediate for A64C ADD/SUB.  */
+  AARCH64_OPND_A64C_IMM8,      /* IMM8 for BICFLGS.  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7728e6e0d92db7c15e6cce80e9d61a0b399e1e5c..5a2896b74d1efbecf211f01b39453169d3c92f82 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * aarch64-opc.c (fields): Add a64c_imm8.
+       (aarch64_print_operand): Add A64C_IMM8.
+       * aarch64-opc.h (aarch64_field_kind): Add a64c_imm8.
+       * aarch64-tbl.h (QL3_A64C_CA_CA_X): New macro.
+       (aarch64_opcode_table): New instructions.
+       (AARCH64_OPERANDS): Add A64C_IMM8.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reg_extended):

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 32908cfd9e1d533679ce3bc3e362389736cabf1b..b23da806ed6e2cbb9b3d2817cb0b888a4a6f0517 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -353,6 +353,7 @@ const aarch64_field fields[] =
     { 10,  5 },  /* Cat2, Capability register in destination for load store pair
                   type instructions.  */
     { 22,  1 },        /* a64c_shift_ai: Shift bit in immediate ADD/SUB.  */
+    { 13,  8 },        /* a64c_imm8: BICFLGS imm8.  */
 };
 
 enum aarch64_operand_class
@@ -3513,6 +3514,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
       snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
       break;
 
+    case AARCH64_OPND_A64C_IMM8:
     case AARCH64_OPND_IDX:
     case AARCH64_OPND_MASK:
     case AARCH64_OPND_IMM:

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index d79ca71a6388119150ba570953ba47b6e2fc5423..4febb55472140dd51ab6fb23abde8f0453367333 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -176,6 +176,7 @@ enum aarch64_field_kind
   FLD_Cat,
   FLD_Cat2,
   FLD_a64c_shift_ai,
+  FLD_a64c_imm8,
 };
 
 /* Field description.  */

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 99ef45fb577874e35015944ed5b005313ef7d97f..bba48c1cd553eee9941c5b90e2e0ae8fb7e116cc 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2402,6 +2402,12 @@
   QLF3(CA, CA, W),             \
 }
 
+/* e.g. BICFLGS <Cd|CSP>, <Cn|CSP>, <Xm>.  */
+#define QL3_A64C_CA_CA_X       \
+{                              \
+  QLF3(CA, CA, X),             \
+}
+
 \f
 /* Opcode table.  */
 
@@ -4035,6 +4041,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   A64C_INSN ("add", 0x02000000, 0xff800000, a64c, OP_A64C_ADD, OP3 (Cad_SP, Can_SP, AIMM), QL3_A64C_CA_CA_NIL, 0),
   A64C_INSN ("add", 0xc2a00000, 0xffe00000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_Rm_EXT), QL3_A64C_CA_CA_R, 0),
   A64C_INSN ("sub", 0x02800000, 0xff800000, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_AIMM), QL3_A64C_CA_CA_NIL, 0),
+  A64C_INSN ("bicflgs", 0xc2e00000, 0xffe01c00, a64c, 0, OP3 (Cad_SP, Can_SP, A64C_IMM8), QL3_A64C_CA_CA_NIL, 0),
+  A64C_INSN ("bicflgs", 0xc2c02800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
   /* TME Instructions.  */
   _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
   _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
@@ -5965,4 +5973,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "an integer register with extension")                            \
     X(IMMEDIATE, ins_aimm, ext_a64c_aimm, "A64C_AIMM", 0,              \
       F(FLD_a64c_shift_ai,FLD_imm12),                                  \
-      "a 12-bit unsigned immediate with optional left shift of 12 bits")
+      "a 12-bit unsigned immediate with optional left shift of 12 bits")\
+    Y(IMMEDIATE, imm, "A64C_IMM8", 0, F(FLD_a64c_imm8),                        \
+      "8-bit unsigned immediate")