* until the voltage change is all done.
*/
clk_en_a = mci_readl(host, CLKENA);
- clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
+ clk_en_a &= ~SDMMC_CLKEN_LOW_PWR;
mci_writel(host, CLKENA, clk_en_a);
mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
SDMMC_CMD_PRV_DAT_WAIT, 0);
} else if (gpio_cd >= 0)
present = gpio_cd;
else
- present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
+ present = (mci_readl(slot->host, CDETECT) & BIT(0))
== 0 ? 1 : 0;
spin_lock_bh(&host->lock);
/* Silent the verbose log if calling from PM context */
if (!force_clkinit)
dev_info(&host->mmc->class_dev,
- "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
- slot->id, host->bus_hz, clock,
+ "Bus speed = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
+ host->bus_hz, clock,
div ? ((host->bus_hz / div) >> 1) :
host->bus_hz, div);
mci_send_cmd(slot, sdmmc_cmd_bits, 0);
/* enable clock; only low power if no SDIO */
- clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
+ clk_en_a = SDMMC_CLKEN_ENABLE;
if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &host->flags))
- clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
+ clk_en_a |= SDMMC_CLKEN_LOW_PWR;
mci_writel(host, CLKENA, clk_en_a);
/* inform CIU */
host->current_speed = clock;
/* Set the current slot bus width */
- mci_writel(host, CTYPE, (slot->ctype << slot->id));
+ mci_writel(host, CTYPE, host->ctype);
}
static void dw_mci_set_data_timeout(struct dw_mci *host,
switch (ios->bus_width) {
case MMC_BUS_WIDTH_4:
- slot->ctype = SDMMC_CTYPE_4BIT;
+ slot->host->ctype = SDMMC_CTYPE_4BIT;
break;
case MMC_BUS_WIDTH_8:
- slot->ctype = SDMMC_CTYPE_8BIT;
+ slot->host->ctype = SDMMC_CTYPE_8BIT;
break;
default:
/* set default 1 bit mode */
- slot->ctype = SDMMC_CTYPE_1BIT;
+ slot->host->ctype = SDMMC_CTYPE_1BIT;
}
regs = mci_readl(slot->host, UHS_REG);
if (ios->timing == MMC_TIMING_MMC_DDR52 ||
ios->timing == MMC_TIMING_UHS_DDR50 ||
ios->timing == MMC_TIMING_MMC_HS400)
- regs |= ((0x1 << slot->id) << 16);
+ regs |= BIT(16);
else
- regs &= ~((0x1 << slot->id) << 16);
+ regs &= ~BIT(16);
mci_writel(slot->host, UHS_REG, regs);
slot->host->timing = ios->timing;
}
set_bit(DW_MMC_CARD_NEED_INIT, &slot->host->flags);
regs = mci_readl(slot->host, PWREN);
- regs |= (1 << slot->id);
+ regs |= BIT(0);
mci_writel(slot->host, PWREN, regs);
break;
case MMC_POWER_ON:
mmc_regulator_disable_vqmmc(mmc);
regs = mci_readl(slot->host, PWREN);
- regs &= ~(1 << slot->id);
+ regs &= ~BIT(0);
mci_writel(slot->host, PWREN, regs);
/* Reset our state machine after powering off */
dw_mci_ctrl_reset(slot->host, SDMMC_CTRL_ALL_RESET_FLAGS);
struct dw_mci *host = slot->host;
const struct dw_mci_drv_data *drv_data = host->drv_data;
u32 uhs;
- u32 v18 = SDMMC_UHS_18V << slot->id;
+ u32 v18 = SDMMC_UHS_18V;
int ret;
if (drv_data && drv_data->switch_voltage)
read_only = gpio_ro;
else
read_only =
- mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
+ mci_readl(slot->host, WRTPRT) & BIT(0) ? 1 : 0;
dev_dbg(&mmc->class_dev, "card is %s\n",
read_only ? "read-only" : "read-write");
* tRSTH >= 1us: RST_n high period
*/
reset = mci_readl(host, RST_N);
- reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
+ reset &= ~SDMMC_RST_HWACTIVE;
mci_writel(host, RST_N, reset);
usleep_range(1, 2);
- reset |= SDMMC_RST_HWACTIVE << slot->id;
+ reset |= SDMMC_RST_HWACTIVE;
mci_writel(host, RST_N, reset);
usleep_range(200, 300);
}
static void dw_mci_prepare_sdio_irq(struct dw_mci_slot *slot, bool prepare)
{
struct dw_mci *host = slot->host;
- const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
+ const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR;
u32 clk_en_a_old;
u32 clk_en_a;
return -ENOMEM;
slot = mmc_priv(mmc);
- slot->id = 0;
- slot->sdio_id = host->sdio_id0 + slot->id;
+ slot->sdio_id = host->sdio_id0;
host->mmc = mmc;
slot->host = host;
host->slot = slot;
* @dto_timer: Timer for broken data transfer over scheme.
* @mmc: The mmc_host representing this dw_mci.
* @flags: Random state bits associated with the host.
+ * @ctype: Card type for this host.
*
* Locking
* =======
#define DW_MMC_CARD_NO_LOW_PWR 2
#define DW_MMC_CARD_NO_USE_HOLD 3
#define DW_MMC_CARD_NEEDS_POLL 4
+ u32 ctype;
};
/* DMA ops for Internal/External DMAC interface */
/**
* struct dw_mci_slot - MMC slot state
* @host: The MMC controller this slot is using.
- * @ctype: Card type for this slot.
* @mrq: mmc_request currently being processed or waiting to be
* processed, or NULL when the slot is idle.
* @queue_node: List node for placing this node in the @queue list of
* @clock: Clock rate configured by set_ios(). Protected by host->lock.
* @__clk_old: The last clock value that was requested from core.
* Keeping track of this helps us to avoid spamming the console.
- * @id: Number of this slot.
* @sdio_id: Number of this slot in the SDIO interrupt registers.
*/
struct dw_mci_slot {
struct dw_mci *host;
- u32 ctype;
-
struct mmc_request *mrq;
struct list_head queue_node;
unsigned int clock;
unsigned int __clk_old;
- int id;
int sdio_id;
};