Since clock lanes under CSIPHY are hard-wired and non-selectable,
it makes sense to remove this port property.
The change follows the same logic as found in commit
336136e197e2
("media: dt-bindings: media: camss: Remove clock-lane property").
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
unevaluatedProperties: false
properties:
- clock-lanes:
- maxItems: 1
-
data-lanes:
minItems: 1
maxItems: 4
- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
required:
- - clock-lanes
- data-lanes
required:
port@0 {
reg = <0>;
csiphy_ep0: endpoint {
- clock-lanes = <7>;
data-lanes = <0 1>;
remote-endpoint = <&sensor_ep>;
};