tools: riscv: Fixed misalignment of CSR related definitions

[ Upstream commit e2cb69263e797c0aa6676bcef23e9e27e44c83b0 ]

The file tools/arch/riscv/include/asm/csr.h borrows from
arch/riscv/include/asm/csr.h, and subsequent modifications
related to CSR should maintain consistency.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
Link: https://patch.msgid.link/20251114071215.816-1-cp0613@linux.alibaba.com
[pjw@kernel.org: dropped Fixes: lines for patches that weren't broken; removed superfluous blank line]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index da3651d329069c18f54ef4b1615ef908b59c956b..6df8b260f0702631ba77e25e535b3d6ebdca7a97 100644 (file)
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -1016,7 +1016,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
                        /* compute hardware counter index */
                        hidx = info->csr - CSR_CYCLE;
 
-               /* check if the corresponding bit is set in sscountovf or overflow mask in shmem */
+               /* check if the corresponding bit is set in scountovf or overflow mask in shmem */
                if (!(overflow & BIT(hidx)))
                        continue;
 

diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h
index 0dfc09254f99af06db831c9b08ebe82c41620a46..1cd824aaa3ba2f1fd10f8e4e0dfd8a6692b6225f 100644 (file)
--- a/tools/arch/riscv/include/asm/csr.h
+++ b/tools/arch/riscv/include/asm/csr.h
@@ -167,7 +167,8 @@
 #define VSIP_TO_HVIP_SHIFT     (IRQ_VS_SOFT - IRQ_S_SOFT)
 #define VSIP_VALID_MASK                ((_AC(1, UL) << IRQ_S_SOFT) | \
                                 (_AC(1, UL) << IRQ_S_TIMER) | \
-                                (_AC(1, UL) << IRQ_S_EXT))
+                                (_AC(1, UL) << IRQ_S_EXT) | \
+                                (_AC(1, UL) << IRQ_PMU_OVF))
 
 /* AIA CSR bits */
 #define TOPI_IID_SHIFT         16
@@ -280,7 +281,7 @@
 #define CSR_HPMCOUNTER30H      0xc9e
 #define CSR_HPMCOUNTER31H      0xc9f
 
-#define CSR_SSCOUNTOVF         0xda0
+#define CSR_SCOUNTOVF          0xda0
 
 #define CSR_SSTATUS            0x100
 #define CSR_SIE                        0x104