Rename pg_crc32c_sse42_choose.c for general purpose

Future commits will consolidate the CPU feature detection functionality
now scattered around in various files, and the CRC "*_choose.c"
files seem to be the natural place for it. For now, just rename in
a separate commit to make it easier to follow the git log. Do the
minimum necessary to keep the build systems functional, and build the
new file pg_cpu_x86.c unconditionally using guards to control the
visibility of its contents, following the model of some more recent
files in src/port.

Limit scope to x86 to reduce the number of moving parts, since the
motivation for doing this now is to clear out some technical debt
before adding AVX2 detection. Arm is left for future work.

Reviewed-by: Zsolt Parragi <zsolt.parragi@percona.com>
Discussion: https://postgr.es/m/CANWCAZbgEUFw7LuYSVeJ=Tj98R5HoOB1Ffeqk3aLvbw5rU5NTw@mail.gmail.com

diff --git a/configure b/configure
index 59894aaa06e6e50749f482c53b5b91b5ff70cb5e..7e6d9cb21396ae482925f7a0a0645543fd740832 100755 (executable)
--- a/configure
+++ b/configure
@@ -18257,7 +18257,7 @@ if test x"$USE_SSE42_CRC32C" = x"1"; then
 
 $as_echo "#define USE_SSE42_CRC32C 1" >>confdefs.h
 
-  PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sse42_choose.o"
+  PG_CRC32C_OBJS="pg_crc32c_sse42.o"
   { $as_echo "$as_me:${as_lineno-$LINENO}: result: SSE 4.2" >&5
 $as_echo "SSE 4.2" >&6; }
 else
@@ -18265,7 +18265,7 @@ else
 
 $as_echo "#define USE_SSE42_CRC32C_WITH_RUNTIME_CHECK 1" >>confdefs.h
 
-    PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sb8.o pg_crc32c_sse42_choose.o"
+    PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sb8.o"
     { $as_echo "$as_me:${as_lineno-$LINENO}: result: SSE 4.2 with runtime check" >&5
 $as_echo "SSE 4.2 with runtime check" >&6; }
   else

diff --git a/configure.ac b/configure.ac
index 24fad757eb5cd8a6bc8ae3bd19540e4a925f9e88..f77ced6ddea0479c46aab7af7e6dc3c30efb41ec 100644 (file)
--- a/configure.ac
+++ b/configure.ac
@@ -2258,12 +2258,12 @@ fi
 AC_MSG_CHECKING([which CRC-32C implementation to use])
 if test x"$USE_SSE42_CRC32C" = x"1"; then
   AC_DEFINE(USE_SSE42_CRC32C, 1, [Define to 1 use Intel SSE 4.2 CRC instructions.])
-  PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sse42_choose.o"
+  PG_CRC32C_OBJS="pg_crc32c_sse42.o"
   AC_MSG_RESULT(SSE 4.2)
 else
   if test x"$USE_SSE42_CRC32C_WITH_RUNTIME_CHECK" = x"1"; then
     AC_DEFINE(USE_SSE42_CRC32C_WITH_RUNTIME_CHECK, 1, [Define to 1 to use Intel SSE 4.2 CRC instructions with a runtime check.])
-    PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sb8.o pg_crc32c_sse42_choose.o"
+    PG_CRC32C_OBJS="pg_crc32c_sse42.o pg_crc32c_sb8.o"
     AC_MSG_RESULT(SSE 4.2 with runtime check)
   else
     if test x"$USE_ARMV8_CRC32C" = x"1"; then

diff --git a/src/port/Makefile b/src/port/Makefile
index 6e3b7d154ed60ccd9632b050e682f9c13c836e1a..47cfea1507daf976af2e9b8033c436d235db1110 100644 (file)
--- a/src/port/Makefile
+++ b/src/port/Makefile
@@ -44,6 +44,7 @@ OBJS = \
        noblock.o \
        path.o \
        pg_bitutils.o \
+       pg_cpu_x86.o \
        pg_localeconv_r.o \
        pg_numa.o \
        pg_popcount_aarch64.o \

diff --git a/src/port/meson.build b/src/port/meson.build
index d7d4e705b89c09422f6026911f41a57dabb484e4..edb2e5632bdfd3891e782949d8f0c6b9e91b0c0f 100644 (file)
--- a/src/port/meson.build
+++ b/src/port/meson.build
@@ -7,6 +7,7 @@ pgport_sources = [
   'noblock.c',
   'path.c',
   'pg_bitutils.c',
+  'pg_cpu_x86.c',
   'pg_localeconv_r.c',
   'pg_numa.c',
   'pg_popcount_aarch64.c',
@@ -86,8 +87,6 @@ replace_funcs_pos = [
   # x86/x64
   ['pg_crc32c_sse42', 'USE_SSE42_CRC32C'],
   ['pg_crc32c_sse42', 'USE_SSE42_CRC32C_WITH_RUNTIME_CHECK'],
-  ['pg_crc32c_sse42_choose', 'USE_SSE42_CRC32C'],
-  ['pg_crc32c_sse42_choose', 'USE_SSE42_CRC32C_WITH_RUNTIME_CHECK'],
   ['pg_crc32c_sb8', 'USE_SSE42_CRC32C_WITH_RUNTIME_CHECK'],
 
   # arm / aarch64

diff --git a/src/port/pg_crc32c_sse42_choose.c b/src/port/pg_cpu_x86.c
similarity index 94%
rename from src/port/pg_crc32c_sse42_choose.c
rename to src/port/pg_cpu_x86.c
index f586476964f7fb361f3228522a6ad284483b2ea5..998a70ffa418d1bbf08003d35ea25d836e6d3f07 100644 (file)
--- a/src/port/pg_crc32c_sse42_choose.c
+++ b/src/port/pg_cpu_x86.c
@@ -1,6 +1,6 @@
 /*-------------------------------------------------------------------------
  *
- * pg_crc32c_sse42_choose.c
+ * pg_cpu_x86.c
  *       Choose between Intel SSE 4.2 and software CRC-32C implementation.
  *
  * On first call, checks if the CPU we're running on supports Intel SSE
@@ -13,13 +13,15 @@
  *
  *
  * IDENTIFICATION
- *       src/port/pg_crc32c_sse42_choose.c
+ *       src/port/pg_cpu_x86.c
  *
  *-------------------------------------------------------------------------
  */
 
 #include "c.h"
 
+#if defined(USE_SSE2) || defined(__i386__)
+
 #if defined(HAVE__GET_CPUID) || defined(HAVE__GET_CPUID_COUNT)
 #include <cpuid.h>
 #endif
@@ -107,3 +109,5 @@ pg_comp_crc32c_choose(pg_crc32c crc, const void *data, size_t len)
 }
 
 pg_crc32c      (*pg_comp_crc32c) (pg_crc32c crc, const void *data, size_t len) = pg_comp_crc32c_choose;
+
+#endif                                                 /* defined(USE_SSE2) || defined(__i386__) */