imx8mp: icore-edimm2.2: Convert to DM_PMIC

Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC
handling.

Changes include:
- Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig.
- Drop legacy SPL I2C and PMIC options.
- Remove manual I2C1 pad setup and legacy power_pca9450_init() usage.
- Use DM-based pmic_get() with the DT node "pmic@25".
- Update PMIC register programming to use struct udevice API.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
index cf2a87a9b9037462422dc15a72f16a349effccaf..13e1070c28e936274c339d91750a162016124a10 100644 (file)
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -22,6 +22,18 @@
        bootph-pre-ram;
 };
 
+&pca9450 {
+       bootph-all;
+};
+
+&pinctrl_i2c1 {
+       bootph-all;
+};
+
+&pinctrl_pmic {
+       bootph-all;
+};
+
 &pinctrl_uart2 {
        bootph-pre-ram;
 };
@@ -63,7 +75,7 @@
 };
 
 &i2c1 {
-       bootph-pre-ram;
+       bootph-all;
 };
 
 &i2c2 {
@@ -118,3 +130,7 @@
        phy-reset-duration = <15>;
        phy-reset-post-delay = <100>;
 };
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+       bootph-all;
+};

diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c
index c1aa28a17bc26797cb387818a885c0a9adf81836..46c581ea51f17af7a5419c6f713b9acad00ebc77 100644 (file)
--- a/board/engicam/imx8mp/spl.c
+++ b/board/engicam/imx8mp/spl.c
@@ -16,9 +16,6 @@
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/ddr.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
@@ -33,36 +30,22 @@ void spl_dram_init(void)
        ddr_init(&dram_timing);
 }
 
-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-       .scl = {
-               .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-               .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-               .gp = IMX_GPIO_NR(5, 14),
-       },
-       .sda = {
-               .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-               .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-               .gp = IMX_GPIO_NR(5, 15),
-       },
-};
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC       0
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
 int power_init_board(void)
 {
-       struct pmic *p;
+       struct udevice *dev;
        int ret;
 
-       ret = power_pca9450_init(I2C_PMIC, 0x25);
-       if (ret)
-               printf("power init failed");
-       p = pmic_get("PCA9450");
-       pmic_probe(p);
+       ret = pmic_get("pmic@25", &dev);
+       if (ret == -ENODEV) {
+               puts("No pmic@25\n");
+               return 0;
+       }
+       if (ret < 0)
+               return ret;
 
        /* BUCKxOUT_DVS0/1 control BUCK123 output */
-       pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+       pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
 
 #ifdef CONFIG_IMX8M_LPDDR4
        /*
@@ -73,22 +56,22 @@ int power_init_board(void)
         */
 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
        /* set DVS0 to 0.85v for special case*/
-       pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+       pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 #else
-       pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+       pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
 #endif
-       pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-       pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+       pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+       pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
 
        /* Kernel uses OD/OD freq for SOC */
        /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
-       pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+       pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
 #elif defined(CONFIG_IMX8M_DDR4)
        /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
-       pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+       pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
 
        /* Set NVCC_DRAM to 1.2v for DDR4 */
-       pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
+       pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
 #endif
 
        return 0;
@@ -136,8 +119,6 @@ void board_init_f(ulong dummy)
 
        enable_tzc380();
 
-       setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
        power_init_board();
 
        /* DDR initialization */

diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 0649d746907793c670305cc86f7813a78fff9e1a..ee55d804980662899f2788b786329814fce80f3c 100644 (file)
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
 CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
@@ -78,8 +75,6 @@ CONFIG_CLK_IMX8MP=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_SUPPORT_EMMC_BOOT=y
@@ -98,12 +93,13 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
-CONFIG_POWER_PCA9450=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y