RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vrem.vv to the
vrem.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_BINARY(T, OP)                                        \
  void                                                                \
  test_vx_binary (T * restrict out, T * restrict in, T x, unsigned n) \
  {                                                                   \
    for (unsigned i = 0; i < n; i++)                                  \
      out[i] = in[i] OP x;                                            \
  }

  DEF_VX_BINARY(int32_t, /)

Before this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vrem.vv v1,v1,v2
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  10   │ test_vx_binary_or_int32_t_case_0:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vrem.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vx_binary_vec_vec_dup): Add new
	case MOD.
	* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
	* config/riscv/vector-iterators.md: Add new op mod.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6a7eb7161b372338a30ea4dfc8c8d73ccc9cb93b..c31ec9e9b4196b34932f1bba411073c09f7545e7 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5569,6 +5569,7 @@ expand_vx_binary_vec_vec_dup (rtx op_0, rtx op_1, rtx op_2,
     case MULT:
     case DIV:
     case UDIV:
+    case MOD:
       icode = code_for_pred_scalar (code, mode);
       break;
     default:

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3fd18c1646dcab505d14f6de0cf83f2cb227dacd..f98072cca7cede991dcf9003ca690263af4ba159 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3949,6 +3949,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
                    {
                    case DIV:
                    case UDIV:
+                   case MOD:
                      *total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
                      break;
                    default:

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 36301b0be6e7b73c0fbf4276d25e20e38bb1e6cf..b1fd607320efb234f3a24bddf7d6edc4ec3181dd 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4042,7 +4042,7 @@
 ])
 
 (define_code_iterator any_int_binop_no_shift_v_vdup [
-  plus minus and ior xor mult div udiv
+  plus minus and ior xor mult div udiv mod
 ])
 
 (define_code_iterator any_int_binop_no_shift_vdup_v [