]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
iommu/arm-smmu: disable PRR on SM8250
authorDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Sat, 5 Jul 2025 16:08:33 +0000 (19:08 +0300)
committerWill Deacon <will@kernel.org>
Mon, 14 Jul 2025 11:18:39 +0000 (12:18 +0100)
On SM8250 / QRB5165-RB5 using PRR bits resets the device, most likely
because of the hyp limitations. Disable PRR support on that platform.

Fixes: 7f2ef1bfc758 ("iommu/arm-smmu: Add support for PRR bit setup")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Rob Clark <robin.clark@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250705-iommu-fix-prr-v2-1-406fecc37cf8@oss.qualcomm.com
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

index 62874b18f6459ad9a8b0542ab81c24e3e745c53d..53d88646476e9f193a6275d9c3ee3d084c215362 100644 (file)
@@ -355,7 +355,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
        priv->set_prr_addr = NULL;
 
        if (of_device_is_compatible(np, "qcom,smmu-500") &&
-                       of_device_is_compatible(np, "qcom,adreno-smmu")) {
+           !of_device_is_compatible(np, "qcom,sm8250-smmu-500") &&
+           of_device_is_compatible(np, "qcom,adreno-smmu")) {
                priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
                priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
        }