phy: qcom-qmp: qserdes-com: Add some more v8 register offsets

Some qserdes-com register offsets for the v8 PHY were previously omitted,
as they were not needed by earlier v8 PHY initialization sequences. Add
these missing v8 register offsets now required to support PCIe QMP PHY on
Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-4-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
index d3b2292257bc521cb66562a5b6bfae8dc8c92cc1..d8ac4c4a2c31615fa7edff2cd4aca86f4f77de66 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
@@ -33,6 +33,7 @@
 #define QSERDES_V8_COM_CP_CTRL_MODE0                   0x070
 #define QSERDES_V8_COM_PLL_RCTRL_MODE0                 0x074
 #define QSERDES_V8_COM_PLL_CCTRL_MODE0                 0x078
+#define QSERDES_V8_COM_CORECLK_DIV_MODE0                       0x07c
 #define QSERDES_V8_COM_LOCK_CMP1_MODE0                 0x080
 #define QSERDES_V8_COM_LOCK_CMP2_MODE0                 0x084
 #define QSERDES_V8_COM_DEC_START_MODE0                 0x088
@@ -40,6 +41,7 @@
 #define QSERDES_V8_COM_DIV_FRAC_START1_MODE0           0x090
 #define QSERDES_V8_COM_DIV_FRAC_START2_MODE0           0x094
 #define QSERDES_V8_COM_DIV_FRAC_START3_MODE0           0x098
+#define QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1           0x09c
 #define QSERDES_V8_COM_VCO_TUNE1_MODE0                 0x0a8
 #define QSERDES_V8_COM_VCO_TUNE2_MODE0                 0x0ac
 #define QSERDES_V8_COM_BG_TIMER                                0x0bc
@@ -47,13 +49,22 @@
 #define QSERDES_V8_COM_SSC_PER1                                0x0cc
 #define QSERDES_V8_COM_SSC_PER2                                0x0d0
 #define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN             0x0dc
+#define QSERDES_V8_COM_CLK_ENABLE1             0x0e0
+#define QSERDES_V8_COM_SYS_CLK_CTRL            0x0e4
+#define QSERDES_V8_COM_PLL_IVCO                0x0f4
 #define QSERDES_V8_COM_SYSCLK_BUF_ENABLE               0x0e8
 #define QSERDES_V8_COM_SYSCLK_EN_SEL                   0x110
 #define QSERDES_V8_COM_RESETSM_CNTRL                   0x118
+#define QSERDES_V8_COM_LOCK_CMP_EN                     0x120
 #define QSERDES_V8_COM_LOCK_CMP_CFG                    0x124
 #define QSERDES_V8_COM_VCO_TUNE_MAP                    0x140
+#define QSERDES_V8_COM_CLK_SELECT                      0x164
 #define QSERDES_V8_COM_CORE_CLK_EN                     0x170
 #define QSERDES_V8_COM_CMN_CONFIG_1                    0x174
+#define QSERDES_V8_COM_CMN_MISC_1                      0x184
+#define QSERDES_V8_COM_CMN_MODE                        0x188
+#define QSERDES_V8_COM_VCO_DC_LEVEL_CTRL                       0x198
+#define QSERDES_V8_COM_PLL_SPARE_FOR_ECO                       0x2b4
 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1            0x1a4
 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2            0x1a8
 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3            0x1ac