clk: renesas: r9a09g077: Add ADC module clocks

Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12-bit
ADC peripherals, each with their own peripheral clock.

For conversion, they use the PCLKL clock.

Add their clocks to the list of module clocks.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250923160524.1096720-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index af3ef6d58c87cdefb2de6c81c0aa9989e542e36d..4ec6c4ddc5f5fd1a84cca3e9a720de6ff831a625 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -188,6 +188,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
        DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
        DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
        DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
+       DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
+       DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
+       DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
        DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
        DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
        DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),