pages = len / mem_page_size + 1;
start_page = start_addr / mem_page_size;
residue = start_addr % mem_page_size;
- base_addr = mac->mem_base_addrs[sel];
+ base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
base_addr += start_page * mem_page_size;
for (pp = 0; pp < pages; pp++) {
u32 val, enum rtw89_mac_mem_sel sel)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
- u32 addr = mac->mem_base_addrs[sel] + offset;
+ u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
rtw89_write32(rtwdev, mac->indir_access_addr, val);
enum rtw89_mac_mem_sel sel)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
- u32 addr = mac->mem_base_addrs[sel] + offset;
+ u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset;
rtw89_write32(rtwdev, mac->filter_model_addr, addr);
return rtw89_read32(rtwdev, mac->indir_access_addr);
#define NAT25_CAM_BASE_ADDR_BE 0x18820000
#define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
#define SEC_CAM_BASE_ADDR_BE 0x18824000
+#define SEC_CAM_BASE_ADDR_BE_8922D 0x1882C000
#define WOW_CAM_BASE_ADDR_BE 0x18828000
#define MLD_TBL_BASE_ADDR_BE 0x18829000
#define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
+static inline
+u32 rtw89_mac_mem_base_addrs(struct rtw89_dev *rtwdev, u8 sel)
+{
+ const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
+
+ if (rtwdev->chip->chip_id == RTL8922D &&
+ sel == RTW89_MAC_MEM_SECURITY_CAM)
+ return SEC_CAM_BASE_ADDR_BE_8922D;
+
+ return mac->mem_base_addrs[sel];
+}
+
static inline
u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
{
start_page = start_addr / mem_page_size;
residue = start_addr % mem_page_size;
- base_addr = mac->mem_base_addrs[sel];
+ base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel);
base_addr += start_page * mem_page_size;
while (cnt < len) {