gpio: mxc: use lock guards for the generic GPIO chip lock

Simplify the code by using lock guards for the bgpio_lock.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250702-gpio-mmio-rework-v2-2-6b77aab684d8@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 4af5a2972d12f68909dd87d9396921c80445f87c..1c37168c8d0a657d7f93067d9ac95cfbd821f757 100644 (file)
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -7,6 +7,7 @@
 // Authors: Daniel Mack, Juergen Beisert.
 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 
+#include <linux/cleanup.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/init.h>
@@ -161,7 +162,6 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct mxc_gpio_port *port = gc->private;
-       unsigned long flags;
        u32 bit, val;
        u32 gpio_idx = d->hwirq;
        int edge;
@@ -200,41 +200,38 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
                return -EINVAL;
        }
 
-       raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
+       scoped_guard(raw_spinlock_irqsave, &port->gc.bgpio_lock) {
+               if (GPIO_EDGE_SEL >= 0) {
+                       val = readl(port->base + GPIO_EDGE_SEL);
+                       if (edge == GPIO_INT_BOTH_EDGES)
+                               writel(val | (1 << gpio_idx),
+                                      port->base + GPIO_EDGE_SEL);
+                       else
+                               writel(val & ~(1 << gpio_idx),
+                                      port->base + GPIO_EDGE_SEL);
+               }
 
-       if (GPIO_EDGE_SEL >= 0) {
-               val = readl(port->base + GPIO_EDGE_SEL);
-               if (edge == GPIO_INT_BOTH_EDGES)
-                       writel(val | (1 << gpio_idx),
-                               port->base + GPIO_EDGE_SEL);
-               else
-                       writel(val & ~(1 << gpio_idx),
-                               port->base + GPIO_EDGE_SEL);
-       }
+               if (edge != GPIO_INT_BOTH_EDGES) {
+                       reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
+                       bit = gpio_idx & 0xf;
+                       val = readl(reg) & ~(0x3 << (bit << 1));
+                       writel(val | (edge << (bit << 1)), reg);
+               }
 
-       if (edge != GPIO_INT_BOTH_EDGES) {
-               reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
-               bit = gpio_idx & 0xf;
-               val = readl(reg) & ~(0x3 << (bit << 1));
-               writel(val | (edge << (bit << 1)), reg);
+               writel(1 << gpio_idx, port->base + GPIO_ISR);
+               port->pad_type[gpio_idx] = type;
        }
 
-       writel(1 << gpio_idx, port->base + GPIO_ISR);
-       port->pad_type[gpio_idx] = type;
-
-       raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
-
        return port->gc.direction_input(&port->gc, gpio_idx);
 }
 
 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 {
        void __iomem *reg = port->base;
-       unsigned long flags;
        u32 bit, val;
        int edge;
 
-       raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
+       guard(raw_spinlock_irqsave)(&port->gc.bgpio_lock);
 
        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
        bit = gpio & 0xf;
@@ -250,12 +247,9 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
        } else {
                pr_err("mxc: invalid configuration for GPIO %d: %x\n",
                       gpio, edge);
-               goto unlock;
+               return;
        }
        writel(val | (edge << (bit << 1)), reg);
-
-unlock:
-       raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
 }
 
 /* handle 32 interrupts in one status register */