Correctly model LL/SC on MIPS.

As the issue with RMW on MIPS does not block execution anymore (see Valgrind
patch r13136), we can switch back to model it through LoadL and StoreC instead
of using incorrect Load and Store.

This will give back correct output to memcheck/tests/atomic_incs on MIPS.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2565

diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 82e4b5a03c7b8a541744a0883d415a283a3da0da..56481d18e508ad952bd5d7376d78d231f40f31e1 100644 (file)
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -2954,10 +2954,10 @@ static void iselStmt(ISelEnv * env, IRStmt * stmt)
 
             HReg r_dst = lookupIRTemp(env, res);
             if (tyRes == Ity_I32) {
-               addInstr(env, MIPSInstr_Load(4, r_dst, r_addr, mode64));
+               addInstr(env, MIPSInstr_LoadL(4, r_dst, r_addr, mode64));
                return;
             } else if (tyRes == Ity_I64 && mode64) {
-               addInstr(env, MIPSInstr_Load(8, r_dst, r_addr, mode64));
+               addInstr(env, MIPSInstr_LoadL(8, r_dst, r_addr, mode64));
                return;
             }
             /* fallthru */ ;
@@ -2971,12 +2971,12 @@ static void iselStmt(ISelEnv * env, IRStmt * stmt)
                                          stmt->Ist.LLSC.storedata);
 
             if (tyData == Ity_I32) {
-               addInstr(env, MIPSInstr_Store(4, r_addr, r_src, mode64));
-               addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+               addInstr(env, mk_iMOVds_RR(r_dst, r_src));
+               addInstr(env, MIPSInstr_StoreC(4, r_addr, r_dst, mode64));
                return;
             } else if (tyData == Ity_I64 && mode64) {
-               addInstr(env, MIPSInstr_Store(8, r_addr, r_src, mode64));
-               addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+               addInstr(env, mk_iMOVds_RR(r_dst, r_src));
+               addInstr(env, MIPSInstr_StoreC(8, r_addr, r_dst, mode64));
                return;
             }
             /* fallthru */