+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/cpu.h>
-#include <linux/cpuhotplug.h>
-#include <linux/interrupt.h>
-#include <linux/sched_clock.h>
-
-#include "timer-of.h"
-
-#define RTTM_DATA 0x0
-#define RTTM_CNT 0x4
-#define RTTM_CTRL 0x8
-#define RTTM_INT 0xc
-
-#define RTTM_CTRL_ENABLE BIT(28)
-#define RTTM_INT_PENDING BIT(16)
-#define RTTM_INT_ENABLE BIT(20)
-
-/*
- * The Otto platform provides multiple 28 bit timers/counters with the following
- * operating logic. If enabled the timer counts up. Per timer one can set a
- * maximum counter value as an end marker. If end marker is reached the timer
- * fires an interrupt. If the timer "overflows" by reaching the end marker or
- * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
- * the timer is in operating mode COUNTER it stops. In mode TIMER it will
- * continue to count up.
- */
-#define RTTM_CTRL_COUNTER 0
-#define RTTM_CTRL_TIMER BIT(24)
-
-#define RTTM_BIT_COUNT 28
-#define RTTM_MIN_DELTA 8
-#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28)
-
-/*
- * Timers are derived from the LXB clock frequency. Usually this is a fixed
- * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
- * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
- * base. The only meaningful frequencies we can achieve from that are 175.000
- * MHz and 153.125 MHz. The greatest common divisor of all explained possible
- * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
- */
-#define RTTM_TICKS_PER_SEC 3125000
-
-struct rttm_cs {
- struct timer_of to;
- struct clocksource cs;
-};
-
-/* Simple internal register functions */
-static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
-{
- iowrite32(counter, base + RTTM_CNT);
-}
-
-static inline unsigned int rttm_get_counter(void __iomem *base)
-{
- return ioread32(base + RTTM_CNT);
-}
-
-static inline void rttm_set_period(void __iomem *base, unsigned int period)
-{
- iowrite32(period, base + RTTM_DATA);
-}
-
-static inline void rttm_disable_timer(void __iomem *base)
-{
- iowrite32(0, base + RTTM_CTRL);
-}
-
-static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)
-{
- iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);
-}
-
-static inline void rttm_ack_irq(void __iomem *base)
-{
- iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);
-}
-
-static inline void rttm_enable_irq(void __iomem *base)
-{
- iowrite32(RTTM_INT_ENABLE, base + RTTM_INT);
-}
-
-static inline void rttm_disable_irq(void __iomem *base)
-{
- iowrite32(0, base + RTTM_INT);
-}
-
-/* Aggregated control functions for kernel clock framework */
-#define RTTM_DEBUG(base) \
- pr_debug("------------- %s %d %08x\n", __func__, \
- smp_processor_id(), (u32)base)
-
-static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *clkevt = dev_id;
- struct timer_of *to = to_timer_of(clkevt);
-
- rttm_ack_irq(to->of_base.base);
- RTTM_DEBUG(to->of_base.base);
- clkevt->event_handler(clkevt);
-
- return IRQ_HANDLED;
-}
-
-static void rttm_stop_timer(void __iomem *base)
-{
- rttm_disable_timer(base);
- rttm_ack_irq(base);
-}
-
-static void rttm_start_timer(struct timer_of *to, u32 mode)
-{
- rttm_set_counter(to->of_base.base, 0);
- rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC);
-}
-
-static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt)
-{
- struct timer_of *to = to_timer_of(clkevt);
-
- RTTM_DEBUG(to->of_base.base);
- rttm_stop_timer(to->of_base.base);
- rttm_set_period(to->of_base.base, delta);
- rttm_start_timer(to, RTTM_CTRL_COUNTER);
-
- return 0;
-}
-
-static int rttm_state_oneshot(struct clock_event_device *clkevt)
-{
- struct timer_of *to = to_timer_of(clkevt);
-
- RTTM_DEBUG(to->of_base.base);
- rttm_stop_timer(to->of_base.base);
- rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
- rttm_start_timer(to, RTTM_CTRL_COUNTER);
-
- return 0;
-}
-
-static int rttm_state_periodic(struct clock_event_device *clkevt)
-{
- struct timer_of *to = to_timer_of(clkevt);
-
- RTTM_DEBUG(to->of_base.base);
- rttm_stop_timer(to->of_base.base);
- rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
- rttm_start_timer(to, RTTM_CTRL_TIMER);
-
- return 0;
-}
-
-static int rttm_state_shutdown(struct clock_event_device *clkevt)
-{
- struct timer_of *to = to_timer_of(clkevt);
-
- RTTM_DEBUG(to->of_base.base);
- rttm_stop_timer(to->of_base.base);
-
- return 0;
-}
-
-static void rttm_setup_timer(void __iomem *base)
-{
- RTTM_DEBUG(base);
- rttm_stop_timer(base);
- rttm_set_period(base, 0);
-}
-
-static u64 rttm_read_clocksource(struct clocksource *cs)
-{
- struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
-
- return (u64)rttm_get_counter(rcs->to.of_base.base);
-}
-
-/* Module initialization part. */
-static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
- .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
- .of_irq = {
- .flags = IRQF_PERCPU | IRQF_TIMER,
- .handler = rttm_timer_interrupt,
- },
- .clkevt = {
- .rating = 400,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_state_periodic = rttm_state_periodic,
- .set_state_shutdown = rttm_state_shutdown,
- .set_state_oneshot = rttm_state_oneshot,
- .set_next_event = rttm_next_event
- },
-};
-
-static int rttm_enable_clocksource(struct clocksource *cs)
-{
- struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
-
- rttm_disable_irq(rcs->to.of_base.base);
- rttm_setup_timer(rcs->to.of_base.base);
- rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER,
- rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC);
-
- return 0;
-}
-
-struct rttm_cs rttm_cs = {
- .to = {
- .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
- },
- .cs = {
- .name = "realtek_otto_timer",
- .rating = 400,
- .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
- .read = rttm_read_clocksource,
- }
-};
-
-static u64 notrace rttm_read_clock(void)
-{
- return (u64)rttm_get_counter(rttm_cs.to.of_base.base);
-}
-
-static int rttm_cpu_starting(unsigned int cpu)
-{
- struct timer_of *to = per_cpu_ptr(&rttm_to, cpu);
-
- RTTM_DEBUG(to->of_base.base);
- to->clkevt.cpumask = cpumask_of(cpu);
- irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask);
- clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC,
- RTTM_MIN_DELTA, RTTM_MAX_DELTA);
- rttm_enable_irq(to->of_base.base);
-
- return 0;
-}
-
-static int __init rttm_probe(struct device_node *np)
-{
- int cpu, cpu_rollback;
- struct timer_of *to;
- int clkidx = num_possible_cpus();
-
- /* Use the first n timers as per CPU clock event generators */
- for_each_possible_cpu(cpu) {
- to = per_cpu_ptr(&rttm_to, cpu);
- to->of_irq.index = to->of_base.index = cpu;
- if (timer_of_init(np, to)) {
- pr_err("%s: setup of timer %d failed\n", __func__, cpu);
- goto rollback;
- }
- rttm_setup_timer(to->of_base.base);
- }
-
- /* Activate the n'th + 1 timer as a stable CPU clocksource. */
- to = &rttm_cs.to;
- to->of_base.index = clkidx;
- timer_of_init(np, to);
- if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) {
- rttm_enable_clocksource(&rttm_cs.cs);
- clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC);
- sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC);
- } else
- pr_err("%s: setup of timer %d as clocksoure failed", __func__, clkidx);
-
- return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING,
- "timer/realtek:online",
- rttm_cpu_starting, NULL);
-rollback:
- pr_err("%s: timer registration failed\n", __func__);
- for_each_possible_cpu(cpu_rollback) {
- if (cpu_rollback == cpu)
- break;
- to = per_cpu_ptr(&rttm_to, cpu_rollback);
- timer_of_cleanup(to);
- }
-
- return -EINVAL;
-}
-
-TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe);
+++ /dev/null
-From 3cc8011171186d906c547bc6f0c1f8e350edc7cf Mon Sep 17 00:00:00 2001
-From: Markus Stockhausen <markus.stockhausen@gmx.de>
-Date: Mon, 3 Oct 2022 14:45:21 +0200
-Subject: [PATCH] realtek: resurrect timer driver
-
-Now that we provide a clock driver for the Reltek SOCs the CPU frequency might
-change on demand. This has direct visible effects during operation
-
-- the CEVT 4K timer is no longer a stable clocksource
-- after CPU frequencies changes time calculation works wrong
-- sched_clock falls back to kernel default interval (100 Hz)
-- timestamps in dmesg have only 2 digits left
-
-[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ...
-[ 0.060000] pid_max: default: 32768 minimum: 301
-[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
-[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
-[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
-[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ...
-
-Looking around where we can start the CEVT timer for RTL930X is a good basis.
-Initially it was developed as a clocksource driver for the broken timer in that
-specific SOC series. Afterwards it was shifted around to the CEVT location,
-got SMP enablement and lost its clocksource feature. So we at least have
-something to copy from. As the timers on these devices are well understood
-the implementation follows this way:
-
-- leave the RTL930X implementation as is
-- provide a new driver for RTL83XX devices only
-- swap RTL930X driver at a later time
-
-Like the clock driver this patch contains a self contained module that is SOC
-independet and already provides full support for the RTL838X, RTL839X and
-RTL930X devices. Some of the new (or reestablished) features are:
-
-- simplified initialization routines
-- SMP setup with CPU hotplug framework
-- derived from LXB clock speed
-- supplied clocksource
-- dedicated register functions for better readability
-- documentation about some caveats
-
-Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
-[remove unused header includes, remove old CONFIG_MIPS dependency, add
-REALTEK_ prefix to driver symbol]
-Signed-off-by: Sander Vanheule <sander@svanheule.net>
-
----
- drivers/clocksource/Kconfig | 12 +++
- drivers/clocksource/Makefile | 1 +
- include/linux/cpuhotplug.h | 1 +
- 3 files changed, 14 insertions(+)
-
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -134,6 +134,17 @@ config RDA_TIMER
- help
- Enables the support for the RDA Micro timer driver.
-
-+config REALTEK_OTTO_TIMER
-+ bool "Clocksource/timer for the Realtek Otto platform"
-+ select COMMON_CLK
-+ select TIMER_OF
-+ help
-+ This driver adds support for the timers found in the Realtek RTL83xx
-+ and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381
-+ and RTL832, as well as chips from the RTL839x series, such as RTL8390
-+ RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series
-+ such as RTL9301, RTL9302 or RTL9303.
-+
- config SUN4I_TIMER
- bool "Sun4i timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -59,6 +59,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi
- obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
- obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
- obj-$(CONFIG_RDA_TIMER) += timer-rda.o
-+obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o
-
- obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
- obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
---- a/include/linux/cpuhotplug.h
-+++ b/include/linux/cpuhotplug.h
-@@ -181,6 +181,7 @@ enum cpuhp_state {
- CPUHP_AP_MARCO_TIMER_STARTING,
- CPUHP_AP_MIPS_GIC_TIMER_STARTING,
- CPUHP_AP_ARC_TIMER_STARTING,
-+ CPUHP_AP_REALTEK_TIMER_STARTING,
- CPUHP_AP_RISCV_TIMER_STARTING,
- CPUHP_AP_CLINT_TIMER_STARTING,
- CPUHP_AP_CSKY_TIMER_STARTING,
projects / thirdparty / openwrt.git / commitdiff
