[AArch64] Handle CSEL of zero_extended operands in rtx costs

	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Handle
	CSEL of zero_extended registers.

From-SVN: r232442

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index edfc0b4a46e4e6c57a27f74bfdd8d3d6de30bc29..d3a632646d4b275aa426b80ddf5bcd7529c603b7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-01-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Handle
+       CSEL of zero_extended registers.
+
 2016-01-15  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case):

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index fee917f135b7e379f203c5cd8583c7f6b5c4ec27..73ef7e5a554cbfdf9f87c1554de7ab5d3724c482 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6145,6 +6145,12 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed)
           || GET_CODE (op1) == NOT
           || (GET_CODE (op1) == PLUS && XEXP (op1, 1) == const1_rtx))
        op1 = XEXP (op1, 0);
+      else if (GET_CODE (op1) == ZERO_EXTEND && GET_CODE (op2) == ZERO_EXTEND)
+       {
+         /* CSEL with zero-extension (*cmovdi_insn_uxtw).  */
+         op1 = XEXP (op1, 0);
+         op2 = XEXP (op2, 0);
+       }
 
       *cost += rtx_cost (op1, VOIDmode, IF_THEN_ELSE, 1, speed);
       *cost += rtx_cost (op2, VOIDmode, IF_THEN_ELSE, 2, speed);