#include <linux/scmi_imx_protocol.h>
#include <linux/types.h>
-#define SCMI_IMX_CTRL_PDM_CLK_SEL 0 /* AON PDM clock sel */
-#define SCMI_IMX_CTRL_MQS1_SETTINGS 1 /* AON MQS settings */
-#define SCMI_IMX_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */
-#define SCMI_IMX_CTRL_SAI3_MCLK 3 /* WAKE SAI3 MCLK */
-#define SCMI_IMX_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */
-#define SCMI_IMX_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */
+#define SCMI_IMX95_CTRL_PDM_CLK_SEL 0 /* AON PDM clock sel */
+#define SCMI_IMX95_CTRL_MQS1_SETTINGS 1 /* AON MQS settings */
+#define SCMI_IMX95_CTRL_SAI1_MCLK 2 /* AON SAI1 MCLK */
+#define SCMI_IMX95_CTRL_SAI3_MCLK 3 /* WAKE SAI3 MCLK */
+#define SCMI_IMX95_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */
+#define SCMI_IMX95_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */
#define SCMI_IMX94_CTRL_PDM_CLK_SEL 0U /*!< AON PDM clock sel */
#define SCMI_IMX94_CTRL_MQS1_SETTINGS 1U /*!< AON MQS settings */
static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = {
.type = TYPE_REG_SM,
- .sm_index = SCMI_IMX_CTRL_MQS1_SETTINGS,
+ .sm_index = SCMI_IMX95_CTRL_MQS1_SETTINGS,
.ctrl_off = 0x88,
.en_mask = BIT(1),
.en_shift = 1,