]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: mac: configure DMA_STOP1 by predefined mask
authorPing-Ke Shih <pkshih@realtek.com>
Thu, 8 Jan 2026 12:03:17 +0000 (20:03 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Tue, 13 Jan 2026 02:30:26 +0000 (10:30 +0800)
For coming chip 8922DE, the DMA channel set is different from existing one,
so use predefined mask to handle the difference.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260108120320.2217402-11-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/mac_be.c
drivers/net/wireless/realtek/rtw89/pci.h
drivers/net/wireless/realtek/rtw89/pci_be.c
drivers/net/wireless/realtek/rtw89/reg.h

index 475d941d41a76517fc797817fc54edc36fc305df..a0e5c99abb17e062efc44c47cf8d6f9f1d38f674 100644 (file)
@@ -365,6 +365,8 @@ static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
 
 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
 {
+       const struct rtw89_chip_info *chip = rtwdev->chip;
+       u32 mask;
        u32 val;
 
        val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
@@ -388,12 +390,12 @@ static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
 
        rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
 
-       rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1,
-                         B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 |
-                         B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
-                         B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
-                         B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 |
-                         B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14);
+       if (chip->chip_id == RTL8922A)
+               mask = B_BE_TX_STOP1_MASK;
+       else
+               mask = B_BE_TX_STOP1_MASK_V1;
+
+       rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, mask);
 
        rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
 }
index 16dfb0e79d7731b34084e507b731c0490acb8307..64c080053fd1d1ea9310d87013b3239def16b352 100644 (file)
 #define R_AX_WP_ADDR_H_SEL8_11 0x133C
 #define R_AX_WP_ADDR_H_SEL12_15 0x1340
 
-#define R_BE_HAXI_DMA_STOP1 0xB010
-#define B_BE_STOP_WPDMA BIT(31)
-#define B_BE_STOP_CH14 BIT(14)
-#define B_BE_STOP_CH13 BIT(13)
-#define B_BE_STOP_CH12 BIT(12)
-#define B_BE_STOP_CH11 BIT(11)
-#define B_BE_STOP_CH10 BIT(10)
-#define B_BE_STOP_CH9 BIT(9)
-#define B_BE_STOP_CH8 BIT(8)
-#define B_BE_STOP_CH7 BIT(7)
-#define B_BE_STOP_CH6 BIT(6)
-#define B_BE_STOP_CH5 BIT(5)
-#define B_BE_STOP_CH4 BIT(4)
-#define B_BE_STOP_CH3 BIT(3)
-#define B_BE_STOP_CH2 BIT(2)
-#define B_BE_STOP_CH1 BIT(1)
-#define B_BE_STOP_CH0 BIT(0)
-#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
-                           B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
-                           B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
-                           B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
-                           B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
-                           B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
-                           B_BE_STOP_CH12)
-
 #define R_BE_CH0_TXBD_NUM_V1 0xB030
 #define R_BE_CH1_TXBD_NUM_V1 0xB032
 #define R_BE_CH2_TXBD_NUM_V1 0xB034
index 95efb1094b6c1c7374525aa470b4d476c59cdf03..148cce0df058e6f10998b160fd2c10351242c6d2 100644 (file)
@@ -322,6 +322,7 @@ static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
 
 static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable)
 {
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
        u32 mask_all;
        u32 val;
 
@@ -330,6 +331,9 @@ static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable)
                   B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
                   B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11;
 
+       /* mask out unsupported channels for certains chips */
+       mask_all &= info->dma_stop1.mask;
+
        val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1);
        val |= B_BE_STOP_CH13 | B_BE_STOP_CH14;
 
index 79c976c25de51ed468b82e3eacf114dbb8b9d65d..bfb1ebcc9fc20affcb38bd9ca3ee34472652f845 100644 (file)
 #define B_BE_STOP_CH2 BIT(2)
 #define B_BE_STOP_CH1 BIT(1)
 #define B_BE_STOP_CH0 BIT(0)
+#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
+                           B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
+                           B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
+                           B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
+                           B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
+                           B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
+                           B_BE_STOP_CH12 | B_BE_STOP_CH13 | \
+                           B_BE_STOP_CH14)
+#define B_BE_TX_STOP1_MASK_V1 (B_BE_STOP_CH0 | B_BE_STOP_CH2 | \
+                              B_BE_STOP_CH4 | B_BE_STOP_CH6 | \
+                              B_BE_STOP_CH8 | B_BE_STOP_CH10 | \
+                              B_BE_STOP_CH12)
 
 #define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C
 #define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)