rs6000: Use standard name {add,sub}v1ti3 for altivec_v{add,sub}uqm

This patch is to adjust define_insn altivec_v{add,sub}uqm
with standard names, as the associated test case shows, w/o
this patch, it ends up with scalar {add,subf}c/{add,subf}e,
the standard names help to exploit v{add,sub}uqm.

gcc/ChangeLog:

	* config/rs6000/altivec.md (altivec_vadduqm): Rename to ...
	(addv1ti3): ... this.
	(altivec_vsubuqm): Rename to ...
	(subv1ti3): ... this.
	* config/rs6000/rs6000-builtins.def (__builtin_altivec_vadduqm):
	Replace bif expander altivec_vadduqm with addv1ti3.
	(__builtin_altivec_vsubuqm): Replace bif expander altivec_vsubuqm with
	subv1ti3.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/p8vector-int128-3.c: New test.

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 687c3c0ac7e150788bde9f30f988353802e23e5f..b6a778ef61792acab998ea9582be172fcecda257 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -4426,7 +4426,7 @@
 ;; ISA 2.07 128-bit binary support to target the VMX/altivec registers without
 ;; having to worry about the register allocator deciding GPRs are better.
 
-(define_insn "altivec_vadduqm"
+(define_insn "addv1ti3"
   [(set (match_operand:V1TI 0 "register_operand" "=v")
        (plus:V1TI (match_operand:V1TI 1 "register_operand" "v")
                   (match_operand:V1TI 2 "register_operand" "v")))]
@@ -4443,7 +4443,7 @@
   "vaddcuq %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
-(define_insn "altivec_vsubuqm"
+(define_insn "subv1ti3"
   [(set (match_operand:V1TI 0 "register_operand" "=v")
        (minus:V1TI (match_operand:V1TI 1 "register_operand" "v")
                    (match_operand:V1TI 2 "register_operand" "v")))]

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 0e9dc05dbcff41b9710349f9a0827c844b05f480..69046fd22442d7465d21662ee8d6176755d9e901 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2012,7 +2012,7 @@
     VADDUDM addv2di3 {}
 
   const vsq __builtin_altivec_vadduqm (vsq, vsq);
-    VADDUQM altivec_vadduqm {}
+    VADDUQM addv1ti3 {}
 
   const vsll __builtin_altivec_vbpermq (vsc, vsc);
     VBPERMQ altivec_vbpermq {}
@@ -2150,7 +2150,7 @@
     VSUBUDM subv2di3 {}
 
   const vsq __builtin_altivec_vsubuqm (vsq, vsq);
-    VSUBUQM altivec_vsubuqm {}
+    VSUBUQM subv1ti3 {}
 
   const vsll __builtin_altivec_vupkhsw (vsi);
     VUPKHSW altivec_vupkhsw {}

diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-3.c
new file mode 100644 (file)
index 0000000..5559410
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-3.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-require-effective-target int128 } */
+
+#ifndef TYPE
+#define TYPE vector __int128_t
+#endif
+
+TYPE
+do_adduqm (TYPE p, TYPE q)
+{
+  return p + q;
+}
+
+TYPE
+do_subuqm (TYPE p, TYPE q)
+{
+  return p - q;
+}
+
+/* { dg-final { scan-assembler-times "vadduqm" 1 } } */
+/* { dg-final { scan-assembler-times "vsubuqm" 1 } } */