clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL

[ Upstream commit 362be5cbaec2a663eb86b7105313368b4a71fc1e ]

According to msm-5.10 the lucid 5lpe PLLs have require slightly
different configuration that trion / lucid PLLs, it doesn't set
PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the
display clock controller on Qualcomm SM8350 platform.

Fixes: 205737fe3345 ("clk: qcom: add support for SM8350 DISPCC")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-2-1149dd8399fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 25a7b4b15c56ab579e2fd64025f9f5a449bbaf74..2720cbc40e0acc0028b06e89854d9b8039d8b591 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -1784,6 +1784,58 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
 
+/**
+ * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
+ *
+ * @pll: clk alpha pll
+ * @regmap: register map
+ * @config: configuration to apply for pll
+ */
+void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                                 const struct alpha_pll_config *config)
+{
+       /*
+        * If the bootloader left the PLL enabled it's likely that there are
+        * RCGs that will lock up if we disable the PLL below.
+        */
+       if (trion_pll_is_enabled(pll, regmap)) {
+               pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
+               return;
+       }
+
+       clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
+       regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
+       clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
+                                    config->config_ctl_val);
+       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
+                                    config->config_ctl_hi_val);
+       clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
+                                    config->config_ctl_hi1_val);
+       clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
+                                       config->user_ctl_val);
+       clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
+                                       config->user_ctl_hi_val);
+       clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
+                                       config->user_ctl_hi1_val);
+       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
+                                       config->test_ctl_val);
+       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
+                                       config->test_ctl_hi_val);
+       clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
+                                       config->test_ctl_hi1_val);
+
+       /* Disable PLL output */
+       regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
+
+       /* Set operation mode to OFF */
+       regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
+
+       /* Place the PLL in STANDBY mode */
+       regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
+
 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
 {
        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index c7055b6c42f1d522346ff2339613c47091cddf59..d89ec4723e2d9c81c4b62f437c0dea98bd1981c2 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -205,6 +205,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 
 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                             const struct alpha_pll_config *config);
+void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                                 const struct alpha_pll_config *config);
 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                                 const struct alpha_pll_config *config);
 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index 43307c8a342caeac08a1523a36feb67b3845c88c..2103e22ca3ddeeee5e0479ef60e7665b1c4e0725 100644 (file)
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -1357,8 +1357,13 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
                disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
        }
 
-       clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
-       clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+       if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
+               clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+               clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+       } else {
+               clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+               clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+       }
 
        /* Enable clock gating for MDP clocks */
        regmap_update_bits(regmap, 0x8000, 0x10, 0x10);