dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
+
+imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo
+
+imx8mp-dhcom-pdk2-overlay-531-100-x21-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo
+
+imx8mp-dhcom-pdk2-overlay-531-100-x22-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo
+
+imx8mp-dhcom-pdk2-overlay-560-300-x12-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo
+
+imx8mp-dhcom-pdk2-overlay-eth1xfast-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-som-overlay-eth1xfast.dtbo
+
+imx8mp-dhcom-pdk2-overlay-eth2xfast-dtbs := \
+ imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
+ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
+
+imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo
+
+imx8mp-dhcom-pdk3-overlay-531-100-x40-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo
+
+imx8mp-dhcom-pdk3-overlay-531-100-x41-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo
+
+imx8mp-dhcom-pdk3-overlay-560-300-x36-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo
+
+imx8mp-dhcom-pdk3-overlay-732-100-x36-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo
+
+imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo
+
+imx8mp-dhcom-pdk3-overlay-eth1xfast-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-som-overlay-eth1xfast.dtbo
+
+imx8mp-dhcom-pdk3-overlay-eth2xfast-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
+ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
+
+imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo
+
+imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31-dtbs := \
+ imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
+ imx8mp-dhcom-som-overlay-eth2xfast.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb \
+ imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \
+ imx8mp-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \
+ imx8mp-dhcom-pdk2-overlay-531-100-x21.dtb \
+ imx8mp-dhcom-pdk2-overlay-531-100-x21.dtbo \
+ imx8mp-dhcom-pdk2-overlay-531-100-x22.dtb \
+ imx8mp-dhcom-pdk2-overlay-531-100-x22.dtbo \
+ imx8mp-dhcom-pdk2-overlay-560-300-x12.dtb \
+ imx8mp-dhcom-pdk2-overlay-560-300-x12.dtbo \
+ imx8mp-dhcom-pdk2-overlay-eth1xfast.dtb \
+ imx8mp-dhcom-pdk2-overlay-eth2xfast.dtb
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb \
+ imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtb \
+ imx8mp-dhcom-pdk3-overlay-505-200-x36-ch101olhlwh.dtbo \
+ imx8mp-dhcom-pdk3-overlay-531-100-x40.dtb \
+ imx8mp-dhcom-pdk3-overlay-531-100-x40.dtbo \
+ imx8mp-dhcom-pdk3-overlay-531-100-x41.dtb \
+ imx8mp-dhcom-pdk3-overlay-531-100-x41.dtbo \
+ imx8mp-dhcom-pdk3-overlay-560-300-x36.dtb \
+ imx8mp-dhcom-pdk3-overlay-560-300-x36.dtbo \
+ imx8mp-dhcom-pdk3-overlay-732-100-x36.dtb \
+ imx8mp-dhcom-pdk3-overlay-732-100-x36.dtbo \
+ imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtb \
+ imx8mp-dhcom-pdk3-overlay-ea-murata-2ae-x20.dtbo \
+ imx8mp-dhcom-pdk3-overlay-eth1xfast.dtb \
+ imx8mp-dhcom-pdk3-overlay-eth2xfast.dtb \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtb \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x29.dtbo \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtb \
+ imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640-x31.dtbo
+
+imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \
+ imx8mp-dhcom-picoitx.dtb \
+ imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
+
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \
+ imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \
+ imx8mp-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo
+
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+
+&display_bl {
+ pwms = <&pwm1 0 5000000 0>;
+};
+
+&i2c_dhpdk_panel {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touch_lvds: touchscreen@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <16384>;
+ touchscreen-size-y = <9600>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&panel {
+ compatible = "chefree,ch101olhlwh-002";
+};
+
+&pwm1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024-2026 Marek Vasut
+ */
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&media_blk_ctrl {
+ /*
+ * Sys PLL3 supplies TC9595 RefClk
+ * Audio PLL2 supplies MEDIA_DISP1_PIX (DSI)
+ * Video PLL1 supplies MEDIA_DISP2_PIX (LVDS)
+ */
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+ <&clk IMX8MP_CLK_MEDIA_APB>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
+ <&clk IMX8MP_AUDIO_PLL2>,
+ <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_AUDIO_PLL2_OUT>,
+ <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <500000000>, <200000000>,
+ <0>, <0>, <0>, <0>;
+};
+
+&tc_bridge {
+ assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
+ <&clk IMX8MP_CLK_CLKOUT2>,
+ <&clk IMX8MP_SYS_PLL3_OUT>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "imx8mp-dhcom-overlay-panel-clock.dtsi"
+
+&{/} {
+ display_bl: display-bl {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
+ status = "okay";
+ };
+
+ panel: panel {
+ backlight = <&display_bl>;
+ power-supply = <®_vdd_3p3v_awo>;
+
+ port {
+ panel_in: endpoint {
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+
+#include "imx8mp-dhcom-overlay-panel-common.dtsi"
+
+&lcdif1 {
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+};
+
+&panel_in {
+ remote-endpoint = <&tc_bridge_out>;
+};
+
+&tc_bridge {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ tc_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include "imx8mp-dhcom-overlay-panel-dpi.dtsi"
+
+&{/} {
+ led {
+ led-0 {
+ /* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */
+ status = "disabled";
+ };
+ };
+};
+
+&i2c_dhpdk_panel {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dhcom_e>;
+ /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */
+ interrupt-parent = <&gpio5>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ };
+};
+
+&display_bl {
+ pwms = <&pwm1 0 5000000 PWM_POLARITY_INVERTED>;
+};
+
+&mipi_dsi {
+ /*
+ * This is DSIM PLL frequency, DSI HS clock lane frequency
+ * is half of the "samsung,burst-clock-frequency" value.
+ */
+ samsung,burst-clock-frequency = <500000000>;
+};
+
+&panel {
+ compatible = "edt,etm0700g0edh6";
+};
+
+&pwm1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+
+#include "imx8mp-dhcom-overlay-panel-common.dtsi"
+
+&ldb_lvds_ch0 {
+ remote-endpoint = <&panel_in>;
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+};
+
+&panel_in {
+ remote-endpoint = <&ldb_lvds_ch0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+ðphypdk { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-lvds.dtsi"
+#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
+
+&{/} {
+ gpio-keys {
+ button-1 {
+ /* BUTTON1 GPIO conflicts with Touchscreen RESET GPIO-B */
+ status = "disabled";
+ };
+ };
+
+ led {
+ led-2 {
+ /* LED7 GPIO conflicts with Touchscreen IRQ GPIO-H */
+ status = "disabled";
+ };
+ };
+};
+
+&media_blk_ctrl {
+ /*
+ * The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>;
+};
+
+&touch_lvds {
+ pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>;
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi"
+#include "imx8mp-pinfunc.h"
+
+&{/} {
+ led {
+ led-0 {
+ /* LED5 GPIO conflicts with Touchscreen IRQ GPIO-E */
+ status = "disabled";
+ };
+ };
+};
+
+&pinctrl_dhcom_e {
+ fsl,pins = <
+ /* GPIO_E */
+ MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x40000000
+ >;
+};
};
};
-&i2c5 {
+i2c_dhpdk_panel: &i2c5 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-lvds.dtsi"
+#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
+#include "imx8mp-pinfunc.h"
+
+&{/} {
+ gpio-keys {
+ button-1 {
+ /* TA2 GPIO conflicts with Touchscreen RESET GPIO-B */
+ status = "disabled";
+ };
+
+ button-2 {
+ /* TA3 GPIO conflicts with Touchscreen IRQ GPIO-C */
+ status = "disabled";
+ };
+ };
+
+ led {
+ led-2 {
+ /* LED2 GPIO conflicts with BL-ON1 GPIO-G */
+ status = "disabled";
+ };
+ };
+};
+
+&media_blk_ctrl {
+ /*
+ * The Chefree CH101OLHLWH-002 panel requires 71.1 MHz LVDS clock.
+ * Set IMX8MP_VIDEO_PLL1 to 497.7 MHz , since 497.7 MHz / 7 = 71.1 MHz .
+ */
+ assigned-clock-rates = <500000000>, <200000000>, <0>, <0>, <0>, <497700000>;
+};
+
+&pinctrl_dhcom_c {
+ fsl,pins = <
+ /* GPIO_C */
+ MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x40000000
+ >;
+};
+
+&touch_lvds {
+ pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_c>;
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2cmuxed0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "microchip,25aa010a", "atmel,at25";
+ reg = <0>;
+ address-width = <8>;
+ pagesize = <16>;
+ size = <128>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-etm0700g0edh6.dtsi"
+
+&{/} {
+ gpio-keys {
+ button-3 {
+ /* TA4 GPIO conflicts with Touchscreen IRQ GPIO-E */
+ status = "disabled";
+ };
+ };
+
+ led {
+ led-2 {
+ /* LED2 GPIO conflicts with BL-ON1 GPIO-G */
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-clock.dtsi"
+
+&lcdif1 {
+ status = "okay";
+};
+
+&mipi_dsi {
+ samsung,burst-clock-frequency = <1000000000>;
+ status = "okay";
+};
+
+&tc_bridge {
+ assigned-clock-rates = <26000000>, <26000000>, <416000000>;
+ toshiba,hpd-pin = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ endpoint {
+ toshiba,pre-emphasis = /bits/ 8 <1 1>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/* This DTO requires HI00106 SoM variant. */
+
+&{/} {
+ led {
+ led-0 {
+ /* LED0 GPIO conflicts with #SDIO_RST GPIO-D */
+ status = "disabled";
+ };
+ };
+};
+
+&uart3 {
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ assigned-clock-rates = <80000000>;
+
+ bluetooth {
+ compatible = "cypress,cyw4373a0-bt";
+ max-speed = <4000000>;
+ };
+};
+
+/* SD slot */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ broken-cd;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ non-removable;
+ vmmc-supply = <&buck4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi@1 { /* muRata 2AE */
+ compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ /*
+ * The "host-wake" interrupt output is by default not
+ * connected to the SoC, but can be connected on to
+ * SoC pin on the carrier board.
+ */
+ reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi"
+
+&mipi_csi_1 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi0_ep: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&ov5640 {
+ powerdown-gpios = <&csi2exp 1 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&csi2exp 0 GPIO_ACTIVE_LOW>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-pdk3-overlay-nxp-spf-29853-c1-ov5640.dtsi"
+
+&mipi_csi_0 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi0_ep: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&ov5640 {
+ powerdown-gpios = <&csi2exp 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&csi2exp 3 GPIO_ACTIVE_LOW>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ camera0_1v5_pwr: regulator-camera0-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-1v5-reg";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ camera0_1v8_pwr: regulator-camera0-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-1v8-reg";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera0_2v8_pwr: regulator-camera0-2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera0-2v8-reg";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+};
+
+&i2cmuxed0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk IMX8MP_CLK_CLKOUT1>;
+ clock-names = "xclk";
+ assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>,
+ <&clk IMX8MP_CLK_CLKOUT1>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ assigned-clock-rates = <24000000>, <24000000>;
+ AVDD-supply = <&camera0_2v8_pwr>;
+ DOVDD-supply = <&camera0_1v8_pwr>;
+ DVDD-supply = <&camera0_1v5_pwr>;
+
+ port {
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi0_ep>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&isi_0 {
+ status = "okay";
+};
#address-cells = <1>;
#size-cells = <0>;
- i2cmuxed0: i2c@0 {
+ i2c_dhpdk_panel: i2cmuxed0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-dhcom-overlay-panel-dpi.dtsi"
+#include "imx8mp-dhcom-overlay-panel-ch101olhlwh.dtsi"
+#include "imx8mp-pinfunc.h"
+
+&{/} {
+ lvds-encoder {
+ compatible = "onnn,fin3385", "lvds-encoder";
+ pclk-sample = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_bridge_in: endpoint {
+ remote-endpoint = <&tc_bridge_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+&mipi_dsi {
+ /*
+ * This is DSIM PLL frequency, DSI HS clock lane frequency
+ * is half of the "samsung,burst-clock-frequency" value.
+ */
+ samsung,burst-clock-frequency = <900000000>;
+};
+
+&panel_in {
+ remote-endpoint = <&lvds_bridge_out>;
+};
+
+&tc_bridge_out {
+ remote-endpoint = <&lvds_bridge_in>;
+};
+
+&touch_lvds {
+ pinctrl-0 = <&pinctrl_dhcom_b &pinctrl_dhcom_h>;
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&iomuxc {
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * B: Touch controller #RESET
+ * H: Touch controller IRQ
+ * I: Yellow led
+ */
+ pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_c &pinctrl_dhcom_d
+ &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g
+ &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+ &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+ &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+ &pinctrl_dhcom_s &pinctrl_dhcom_int>;
+};
status = "disabled";
};
+i2c_dhpdk_panel: &i2c5 {
+};
+
&irqsteer_hdmi {
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&eqos { /* First ethernet */
+ pinctrl-0 = <&pinctrl_eqos_rmii>;
+ phy-handle = <ðphy0f>;
+ phy-mode = "rmii";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+ðphy0g { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
+
+ðphy0f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
+ status = "disabled";
+};
+
+/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
+
+&hdmi_blk_ctrl {
+ status = "disabled";
+};
+
+&hdmi_pvi {
+ status = "disabled";
+};
+
+&hdmi_tx {
+ status = "disabled";
+};
+
+&hdmi_tx_phy {
+ status = "disabled";
+};
+
+&irqsteer_hdmi {
+ status = "disabled";
+};
+
+&lcdif3 {
+ status = "disabled";
+};
+
+&pcie_phy {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&uart2 {
+ bluetooth {
+ status = "disabled";
+ };
+};
+
+&usb_dwc3_0 {
+ maximum-speed = "high-speed";
+};
+
+&usb_dwc3_1 {
+ maximum-speed = "high-speed";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&usdhc1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023-2026 Marek Vasut
+ */
+#include "imx8mp-dhcom-som-overlay-eth1xfast.dtso"
+
+/* Dual RMII 100/Full Fast ethernet on this SoM variant. */
+
+ðphy1f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&fec { /* Second ethernet */
+ pinctrl-0 = <&pinctrl_fec_rmii>;
+ phy-handle = <ðphy1f>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
+};
+
+/* Resistive touch controller not populated on this one SoM variant. */
+&touch_som {
+ status = "disabled";
+};
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2021-2026 Marek Vasut
*/
#include "imx8mp.dtsi"
};
};
- touchscreen@49 {
+ touch_som: touchscreen@49 {
compatible = "ti,tsc2004";
reg = <0x49>;
interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
projects / thirdparty / linux.git / commitdiff
