RISC-V: Fix one incorrect match operand for RVV reduction

There are 2 of the RVV reduction pattern mask operand takes
vector_merge_operand instead of vector_mask_operand by mistake. This
patch would like to fix this.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/vector.md: Fix incorrect match_operand.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests.
	* gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fcff3ee3a173fdf6edab3e028b448ebfbfa09db7..f745888127c89b4578c78a69f74932f778577fdc 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7915,7 +7915,7 @@
        (unspec:VSF_LMUL1
          [(unspec:VSF_LMUL1
            [(unspec:<VHF:VM>
-             [(match_operand:<VHF:VM> 1 "vector_merge_operand"  "vmWc1,vmWc1")
+             [(match_operand:<VHF:VM> 1 "vector_mask_operand"   "vmWc1,vmWc1")
               (match_operand          5 "vector_length_operand" "   rK,   rK")
               (match_operand          6 "const_int_operand"     "    i,    i")
               (match_operand          7 "const_int_operand"     "    i,    i")
@@ -7937,7 +7937,7 @@
        (unspec:VDF_LMUL1
          [(unspec:VDF_LMUL1
            [(unspec:<VSF:VM>
-             [(match_operand:<VSF:VM>  1 "vector_merge_operand"  "vmWc1,vmWc1")
+             [(match_operand:<VSF:VM>  1 "vector_mask_operand"   "vmWc1,vmWc1")
               (match_operand           5 "vector_length_operand" "   rK,   rK")
               (match_operand           6 "const_int_operand"     "    i,    i")
               (match_operand           7 "const_int_operand"     "    i,    i")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
index d83eea925a7b6ee517395a79ef9e2846f1f47138..a903dde34d17f54b3703fee207a520bf43a5b6e9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
@@ -3,5 +3,5 @@
 
 #include "pr110299-1.h"
 
-/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
index cdcde1b89a4cd7342ad75175197087710933f256..1254ace58eb23ff19bebe9793e8900d11632c1cc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
@@ -4,5 +4,5 @@
 #include "pr110299-1.h"
 #include "pr110299-2.h"
 
-/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
-/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */