AVR: Add an RTL peephole to tweak lower_reg:QI o= cst.

For operations like  X o= CST, regalloc may spill l-reg X to a d-reg:
   D =  X
   D o= CST
   X =  D
where it is better to instead
   D =  CST
   X o= D
This patch adds an according RTL peephole.

gcc/
	* config/avr/avr.md: Add a peephole2 that improves bit operations
	with a lower register and a constant.

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index aae8a696a63819d3ffc12e4987bec9d305997983..80ad7e97ac935c4cc81bd3af28da0880c22fff02 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -4745,6 +4745,37 @@
               (clobber (reg:CC REG_CC))])])
 
 
+;; For operations like  X o= CST, regalloc may spill l-reg X to a d-reg:
+;;    D =  X
+;;    D o= CST
+;;    X =  D
+;; where it is better to instead
+;;    D =  CST
+;;    X o= D
+(define_peephole2
+  [; Move l-reg to d-reg for the purpose of BITOP.
+   (parallel [(set (match_operand:ALL1 0 "d_register_operand")
+                   (match_operand:ALL1 1 "l_register_operand"))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (match_dup 0)
+                   (bitop:ALL1 (match_dup 0)
+                               (match_operand:ALL1 2 "const_operand")))
+              (clobber (reg:CC REG_CC))])
+   ; Move d-reg result back to l-reg.
+   (parallel [(set (match_dup 1)
+                   (match_dup 0))
+              (clobber (reg:CC REG_CC))])]
+  "peep2_reg_dead_p (3, operands[0])"
+  [; "movqi_insn"
+   (parallel [(set (match_dup 0)
+                   (match_dup 2))
+              (clobber (reg:CC REG_CC))])
+   (parallel [(set (match_dup 1)
+                   (bitop:ALL1 (match_dup 1)
+                               (match_dup 0)))
+              (clobber (reg:CC REG_CC))])])
+
+
 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
 ;; swap