More AltiVec: shifts and rotates

 - vrl*, vsl*, vsr*

git-svn-id: svn://svn.valgrind.org/vex/trunk@1402

diff --git a/VEX/priv/guest-ppc32/toIR.c b/VEX/priv/guest-ppc32/toIR.c
index dd921161d0ec14b74a187493cd55cdb4ff0f834d..9386a506b319da8dcb337282247299cd42efff21 100644 (file)
--- a/VEX/priv/guest-ppc32/toIR.c
+++ b/VEX/priv/guest-ppc32/toIR.c
@@ -5645,61 +5645,73 @@ static Bool dis_av_shift ( UInt theInstr )
    /* Rotate */
    case 0x004: // vrlb (Rotate Left Integer B, AV p234)
       DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Rotl8x16, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x044: // vrlh (Rotate Left Integer HW, AV p235)
       DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Rotl16x8, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x084: // vrlw (Rotate Left Integer W, AV p236)
       DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Rotl32x4, mkexpr(vA), mkexpr(vB)) );
+      break;
 
 
    /* Shift Left */
    case 0x104: // vslb (Shift Left Integer B, AV p240)
       DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x144: // vslh (Shift Left Integer HW, AV p242)
       DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x184: // vslw (Shift Left Integer W, AV p244)
       DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) );
+      break;
 
-   case 0x1C4: // vsl (Shift Left, AV p239)
+   case 0x1C4: { // vsl (Shift Left, AV p239)
       DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
-
-   case 0x40C: // vslo (Shift Left by Octet, AV p243)
+      IRTemp sh = newTemp(Ity_I8);
+      assign( sh, binop(Iop_And8, mkU8(0x7),
+                        unop(Iop_32to8,
+                             unop(Iop_V128to32, mkexpr(vB)))) );
+      putVReg( vD_addr,
+               binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+      break;
+   }
+   case 0x40C: { // vslo (Shift Left by Octet, AV p243)
       DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      IRTemp sh = newTemp(Ity_I8);
+      assign( sh, binop(Iop_And8, mkU8(0x78),
+                        unop(Iop_32to8,
+                             unop(Iop_V128to32, mkexpr(vB)))) );
+      putVReg( vD_addr,
+               binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+      break;
+   }
+
 
    /* Shift Right */
    case 0x204: // vsrb (Shift Right B, AV p256)
       DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x244: // vsrh (Shift Right HW, AV p257)
       DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x284: // vsrw (Shift Right W, AV p259)
       DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x2C4: { // vsr (Shift Right, AV p251)
       DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
@@ -5713,23 +5725,29 @@ static Bool dis_av_shift ( UInt theInstr )
    }
    case 0x304: // vsrab (Shift Right Algebraic B, AV p253)
       DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x344: // vsrah (Shift Right Algebraic HW, AV p254)
       DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) );
+      break;
 
    case 0x384: // vsraw (Shift Right Algebraic W, AV p255)
       DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) );
+      break;
 
-   case 0x44C: // vsro (Shift Right by Octet, AV p258)
+   case 0x44C: { // vsro (Shift Right by Octet, AV p258)
       DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      IRTemp sh = newTemp(Ity_I8);
+      assign( sh, binop(Iop_And8, mkU8(0x78),
+                        unop(Iop_32to8,
+                             unop(Iop_V128to32, mkexpr(vB)))) );
+      putVReg( vD_addr,
+               binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) );
+      break;
+   }
 
    default:
       vex_printf("dis_av_shift(PPC32)(opc2)\n");
@@ -6054,7 +6072,6 @@ static Bool dis_av_pack ( UInt theInstr )
       return False;
    }
 
-
    IRTemp signs = newTemp(Ity_V128);
    IRTemp zeros = newTemp(Ity_V128);
    assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );

diff --git a/VEX/priv/host-ppc32/isel.c b/VEX/priv/host-ppc32/isel.c
index 7a217e302a2df54f418ffe83d3f7cceef58edc01..41d7e6eef2ecf9dcefe966cc9ddcbf2977ca33df 100644 (file)
--- a/VEX/priv/host-ppc32/isel.c
+++ b/VEX/priv/host-ppc32/isel.c
@@ -3275,13 +3275,6 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
 //..          return dst;
 //..       }
 
-//..       case Iop_QNarrow32Sx4: 
-//..          op = Xsse_PACKSSD; arg1isEReg = True; goto do_SseReRg;
-//..       case Iop_QNarrow16Sx8: 
-//..          op = Xsse_PACKSSW; arg1isEReg = True; goto do_SseReRg;
-//..       case Iop_QNarrow16Ux8: 
-//..          op = Xsse_PACKUSW; arg1isEReg = True; goto do_SseReRg;
-
       case Iop_AndV128:    op = Pav_AND;      goto do_AvBin;
       case Iop_OrV128:     op = Pav_OR;       goto do_AvBin;
       case Iop_XorV128:    op = Pav_XOR;      goto do_AvBin;
@@ -3293,27 +3286,12 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
-//..       case Iop_Add8x16:    op = Xsse_ADD8;     goto do_SseReRg;
-//..       case Iop_Add64x2:    op = Xsse_ADD64;    goto do_SseReRg;
-//..       case Iop_QAdd8Sx16:  op = Xsse_QADD8S;   goto do_SseReRg;
-//..       case Iop_QAdd16Sx8:  op = Xsse_QADD16S;  goto do_SseReRg;
-//..       case Iop_QAdd8Ux16:  op = Xsse_QADD8U;   goto do_SseReRg;
-//..       case Iop_QAdd16Ux8:  op = Xsse_QADD16U;  goto do_SseReRg;
-//..       case Iop_Avg8Ux16:   op = Xsse_AVG8U;    goto do_SseReRg;
-//..       case Iop_Avg16Ux8:   op = Xsse_AVG16U;   goto do_SseReRg;
-//..       case Iop_CmpEQ8x16:  op = Xsse_CMPEQ8;   goto do_SseReRg;
-//..       case Iop_CmpEQ16x8:  op = Xsse_CMPEQ16;  goto do_SseReRg;
-//..       case Iop_CmpEQ32x4:  op = Xsse_CMPEQ32;  goto do_SseReRg;
-//..       case Iop_CmpGT8Sx16: op = Xsse_CMPGT8S;  goto do_SseReRg;
-//..       case Iop_CmpGT16Sx8: op = Xsse_CMPGT16S; goto do_SseReRg;
-//..       case Iop_CmpGT32Sx4: op = Xsse_CMPGT32S; goto do_SseReRg;
 //..       case Iop_Mul16x8:    op = Xsse_MUL16;    goto do_SseReRg;
-//..       case Iop_Sub64x2:    op = Xsse_SUB64;    goto do_SseReRg;
-//..       case Iop_QSub8Sx16:  op = Xsse_QSUB8S;   goto do_SseReRg;
-//..       case Iop_QSub16Sx8:  op = Xsse_QSUB16S;  goto do_SseReRg;
-//..       case Iop_QSub8Ux16:  op = Xsse_QSUB8U;   goto do_SseReRg;
-//..       case Iop_QSub16Ux8:  op = Xsse_QSUB16U;  goto do_SseReRg;
 
+      case Iop_Shl8x16:    op = Pav_SHL;    goto do_AvBin8x16;
+      case Iop_Shr8x16:    op = Pav_SHR;    goto do_AvBin8x16;
+      case Iop_Sar8x16:    op = Pav_SAR;    goto do_AvBin8x16;
+      case Iop_Rotl8x16:   op = Pav_ROTL;   goto do_AvBin8x16;
       case Iop_InterleaveHI8x16: op = Pav_MRGHI;  goto do_AvBin8x16;
       case Iop_InterleaveLO8x16: op = Pav_MRGLO;  goto do_AvBin8x16;
       case Iop_Add8x16:    op = Pav_ADDUM;  goto do_AvBin8x16;
@@ -3339,6 +3317,10 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
+      case Iop_Shl16x8:    op = Pav_SHL;    goto do_AvBin16x8;
+      case Iop_Shr16x8:    op = Pav_SHR;    goto do_AvBin16x8;
+      case Iop_Sar16x8:    op = Pav_SAR;    goto do_AvBin16x8;
+      case Iop_Rotl16x8:   op = Pav_ROTL;   goto do_AvBin16x8;
       case Iop_Narrow16Ux8:      op = Pav_PACKUUM; goto do_AvBin16x8;
       case Iop_QNarrow16Ux8:     op = Pav_PACKUUS; goto do_AvBin16x8;
       case Iop_QNarrow16Sx8:     op = Pav_PACKSSS; goto do_AvBin16x8;
@@ -3371,6 +3353,10 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
+      case Iop_Shl32x4:    op = Pav_SHL;    goto do_AvBin32x4;
+      case Iop_Shr32x4:    op = Pav_SHR;    goto do_AvBin32x4;
+      case Iop_Sar32x4:    op = Pav_SAR;    goto do_AvBin32x4;
+      case Iop_Rotl32x4:   op = Pav_ROTL;   goto do_AvBin32x4;
       case Iop_Narrow32Ux4:      op = Pav_PACKUUM; goto do_AvBin32x4;
       case Iop_QNarrow32Ux4:     op = Pav_PACKUUS; goto do_AvBin32x4;
       case Iop_QNarrow32Sx4:     op = Pav_PACKSSS; goto do_AvBin32x4;
@@ -3403,30 +3389,6 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
-//..       do_SseReRg: {
-//..          HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1);
-//..          HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
-//..          HReg dst = newVRegV(env);
-//..          if (op != Xsse_OR && op != Xsse_AND && op != Xsse_XOR)
-//..             REQUIRE_SSE2;
-//..          if (arg1isEReg) {
-//..             addInstr(env, mk_vMOVsd_RR(arg2, dst));
-//..             addInstr(env, X86Instr_SseReRg(op, arg1, dst));
-//..          } else {
-//..             addInstr(env, mk_vMOVsd_RR(arg1, dst));
-//..             addInstr(env, X86Instr_SseReRg(op, arg2, dst));
-//..          }
-//..          return dst;
-//..       }
-//.. 
-//..       case Iop_ShlN16x8: op = Xsse_SHL16; goto do_SseShift;
-//..       case Iop_ShlN32x4: op = Xsse_SHL32; goto do_SseShift;
-//..       case Iop_ShlN64x2: op = Xsse_SHL64; goto do_SseShift;
-//..       case Iop_SarN16x8: op = Xsse_SAR16; goto do_SseShift;
-//..       case Iop_SarN32x4: op = Xsse_SAR32; goto do_SseShift;
-//..       case Iop_ShrN16x8: op = Xsse_SHR16; goto do_SseShift;
-//..       case Iop_ShrN64x2: op = Xsse_SHR64; goto do_SseShift;
-
       case Iop_ShlN8x16: op = Pav_SHL; goto do_AvShift8x16;
       case Iop_SarN8x16: op = Pav_SAR; goto do_AvShift8x16;
       do_AvShift8x16: {