reg = <0x0 0x10220 0x0 0x140>;
amlogic,has-chip-id;
};
+
+ sd_emmc_a: mmc@88000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x88000 0x0 0x800>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
+ <&clkc_periphs CLKID_SD_EMMC_A>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
+ assigned-clock-parents = <&xtal>;
+ status = "disabled";
+ };
+
+ sd_emmc_b: mmc@8a000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
+ <&clkc_periphs CLKID_SD_EMMC_B>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
+ assigned-clock-parents = <&xtal>;
+ status = "disabled";
+ };
+
+ sd_emmc_c: mmc@8c000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x8c000 0x0 0x800>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
+ <&clkc_periphs CLKID_SD_EMMC_C>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
+ assigned-clock-parents = <&xtal>;
+ status = "disabled";
+ };
};
};