clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll

[ Upstream commit d40371a1c963db688b37826adaf5ffdafb0862a1 ]

According to Reference Manual of i.MX8MP
The parent clock of "earc_phy" is "sai_pll_out_div2",
The parent clock of "audpll" is "osc_24m".

Add CLK_GATE_PARENT() macro for usage of specifying parent clock.

Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1718350923-21392-6-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
index 55ed211a5e0b18f015ae66c9d75f2918a9e716aa..ab2a028b3027d38196ad6a8865e4304e10ca7c79 100644 (file)
--- a/drivers/clk/imx/clk-imx8mp-audiomix.c
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -146,6 +146,15 @@ static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
                PDM_SEL, 2, 0                                           \
        }
 
+#define CLK_GATE_PARENT(gname, cname, pname)                                           \
+       {                                                               \
+               gname"_cg",                                             \
+               IMX8MP_CLK_AUDIOMIX_##cname,                            \
+               { .fw_name = pname, .name = pname }, NULL, 1,           \
+               CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32),      \
+               1, IMX8MP_CLK_AUDIOMIX_##cname % 32                     \
+       }
+
 struct clk_imx8mp_audiomix_sel {
        const char                      *name;
        int                             clkid;
@@ -163,14 +172,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
        CLK_GATE("earc", EARC_IPG),
        CLK_GATE("ocrama", OCRAMA_IPG),
        CLK_GATE("aud2htx", AUD2HTX_IPG),
-       CLK_GATE("earc_phy", EARC_PHY),
+       CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
        CLK_GATE("sdma2", SDMA2_ROOT),
        CLK_GATE("sdma3", SDMA3_ROOT),
        CLK_GATE("spba2", SPBA2_ROOT),
        CLK_GATE("dsp", DSP_ROOT),
        CLK_GATE("dspdbg", DSPDBG_ROOT),
        CLK_GATE("edma", EDMA_ROOT),
-       CLK_GATE("audpll", AUDPLL_ROOT),
+       CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
        CLK_GATE("mu2", MU2_ROOT),
        CLK_GATE("mu3", MU3_ROOT),
        CLK_PDM,