]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/xe/cri: Enable I2C controller
authorRaag Jadav <raag.jadav@intel.com>
Fri, 28 Nov 2025 08:44:14 +0000 (14:14 +0530)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 12 Dec 2025 16:49:22 +0000 (08:49 -0800)
Enable I2C controller for Crescent Island and while at it, rely on
has_i2c flag instead of manual platform checks.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20251128084414.306265-1-raag.jadav@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
drivers/gpu/drm/xe/xe_device_types.h
drivers/gpu/drm/xe/xe_i2c.c
drivers/gpu/drm/xe/xe_pci.c
drivers/gpu/drm/xe/xe_pci_types.h

index 842b33444944ea808b1babbcdb33e842379e7847..ffce1dcca9828f6f0c9657d127088c706fd81d91 100644 (file)
@@ -304,6 +304,8 @@ struct xe_device {
                u8 has_heci_cscfi:1;
                /** @info.has_heci_gscfi: device has heci gscfi */
                u8 has_heci_gscfi:1;
+               /** @info.has_i2c: Device has I2C controller */
+               u8 has_i2c:1;
                /** @info.has_late_bind: Device has firmware late binding support */
                u8 has_late_bind:1;
                /** @info.has_llc: Device has a shared CPU+GPU last level cache */
index 0b5452be0c8736b5a6a1258b33e3fa93a0d12cc1..8eccbae05705eece09bf6f705db4bc4a20d90207 100644 (file)
@@ -319,7 +319,7 @@ int xe_i2c_probe(struct xe_device *xe)
        struct xe_i2c *i2c;
        int ret;
 
-       if (xe->info.platform != XE_BATTLEMAGE)
+       if (!xe->info.has_i2c)
                return 0;
 
        if (IS_SRIOV_VF(xe))
index 16b3eb247439b5edf99cbaf5eb8a7c6d0f7f365b..0a4e9d59859e8b3f0302acc986a256cdc98ed583 100644 (file)
@@ -367,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
        .has_mbx_power_limits = true,
        .has_gsc_nvm = 1,
        .has_heci_cscfi = 1,
+       .has_i2c = true,
        .has_late_bind = true,
        .has_sriov = true,
        .has_mem_copy_instr = true,
@@ -412,6 +413,7 @@ static const struct xe_device_desc cri_desc = {
        .dma_mask_size = 52,
        .has_display = false,
        .has_flat_ccs = false,
+       .has_i2c = true,
        .has_mbx_power_limits = true,
        .has_mert = true,
        .has_sriov = true,
@@ -678,6 +680,7 @@ static int xe_info_init_early(struct xe_device *xe,
        xe->info.has_gsc_nvm = desc->has_gsc_nvm;
        xe->info.has_heci_gscfi = desc->has_heci_gscfi;
        xe->info.has_heci_cscfi = desc->has_heci_cscfi;
+       xe->info.has_i2c = desc->has_i2c;
        xe->info.has_late_bind = desc->has_late_bind;
        xe->info.has_llc = desc->has_llc;
        xe->info.has_mert = desc->has_mert;
index b06c108e25e693e4e4cb0a0930f22bab4f845cf5..bfac64d04dee9554b88bd5e4ade71e1a48bf8898 100644 (file)
@@ -44,6 +44,7 @@ struct xe_device_desc {
        u8 has_gsc_nvm:1;
        u8 has_heci_gscfi:1;
        u8 has_heci_cscfi:1;
+       u8 has_i2c:1;
        u8 has_late_bind:1;
        u8 has_llc:1;
        u8 has_mbx_power_limits:1;