-From ee980d96b6ecd385691f101e641f3e15513ce8c3 Mon Sep 17 00:00:00 2001
+From 579839c9548cf2a85e873ad787bc2fa6610bf8ab Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 25 May 2025 20:28:34 +0200
-Subject: [PATCH 3/5] pinctrl: airoha: convert PHY LED GPIO to macro
+Date: Fri, 7 Nov 2025 00:57:05 +0100
+Subject: [PATCH 2/5] pinctrl: airoha: convert PHY LED GPIO to macro
PHY LED GPIO pinctrl struct definition is very similar across the
different 4 PHY and 2 LED and it can be generelized to a macro.
To reduce code size, convert them to a common macro.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 570 ++++------------------
- 1 file changed, 82 insertions(+), 488 deletions(-)
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 588 ++++------------------
+ 1 file changed, 100 insertions(+), 488 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
-@@ -1478,516 +1478,110 @@ static const struct airoha_pinctrl_func_
+@@ -1478,516 +1478,128 @@ static const struct airoha_pinctrl_func_
},
};
-+#define AIROHA_PINCTRL_PHY_LED(gpio, mux_val, map_mask, map_val) \
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ }, \
+ .regmap_size = 2, \
+ }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
++ { \
++ .name = (gpio), \
++ .regmap[0] = { \
++ AIROHA_FUNC_MUX, \
++ REG_GPIO_2ND_I2C_MODE, \
++ (mux_val), \
++ (mux_val), \
++ }, \
++ .regmap[1] = { \
++ AIROHA_FUNC_MUX, \
++ REG_LAN_LED1_MAPPING, \
++ (map_mask), \
++ (map_val), \
++ }, \
++ .regmap_size = 2, \
++ }
+
static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
- {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
- },
- .regmap_size = 2,
- },
-+ AIROHA_PINCTRL_PHY_LED("gpio33", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio34", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio35", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio42", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
-From cc92581b44cc3a6821c540ddbe27d4c009a7d312 Mon Sep 17 00:00:00 2001
+From 3ffeb17a9a27a668efb6fbd074835e187910a9bb Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 25 May 2025 21:32:25 +0200
+Date: Fri, 7 Nov 2025 00:57:08 +0100
Subject: [PATCH 5/5] pinctrl: airoha: add support for Airoha AN7583 PINs
Add all the required entry to add suppot for Airoha AN7583 PINs.
reduce code duplication.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
- drivers/pinctrl/mediatek/pinctrl-airoha.c | 733 ++++++++++++++++++++++
- 1 file changed, 733 insertions(+)
+ drivers/pinctrl/mediatek/pinctrl-airoha.c | 747 +++++++++++++++++++++-
+ 1 file changed, 740 insertions(+), 7 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
"gpio45", "gpio46" };
+static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
++ "gpio3", "gpio4" };
+static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
++ "gpio3", "gpio4" };
+static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
++ "gpio3", "gpio4" };
+static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
-+ "gpio3", "gpio4" };
++ "gpio3", "gpio4" };
+static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
++ "gpio10", "gpio11" };
+static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
++ "gpio10", "gpio11" };
+static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
++ "gpio10", "gpio11" };
+static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
-+ "gpio10", "gpio11" };
++ "gpio10", "gpio11" };
static const struct airoha_pinctrl_func_group pon_func_group[] = {
{
/* PWM */
#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
{ \
-@@ -1255,6 +1614,94 @@ static const struct airoha_pinctrl_func_
- LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+@@ -1273,6 +1632,94 @@ static const struct airoha_pinctrl_func_
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN0_LED0_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio2", GPIO_LAN1_LED0_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio3", GPIO_LAN2_LED0_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
-+ AIROHA_PINCTRL_PHY_LED("gpio4", GPIO_LAN3_LED0_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++ AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
-+ AIROHA_PINCTRL_PHY_LED("gpio1", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++ AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
-+ AIROHA_PINCTRL_PHY_LED("gpio8", GPIO_LAN0_LED1_MODE_MASK,
-+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio9", GPIO_LAN1_LED1_MODE_MASK,
-+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio10", GPIO_LAN2_LED1_MODE_MASK,
-+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
-+ AIROHA_PINCTRL_PHY_LED("gpio11", GPIO_LAN3_LED1_MODE_MASK,
-+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
-@@ -1281,6 +1728,31 @@ static const struct airoha_pinctrl_func
+@@ -1299,6 +1746,31 @@ static const struct airoha_pinctrl_func
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
-@@ -1342,6 +1814,62 @@ static const struct airoha_pinctrl_conf
+@@ -1360,6 +1832,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
-@@ -1403,6 +1931,62 @@ static const struct airoha_pinctrl_conf
+@@ -1421,6 +1949,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
-@@ -1464,6 +2048,62 @@ static const struct airoha_pinctrl_conf
+@@ -1482,6 +2066,62 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
-@@ -1525,12 +2165,73 @@ static const struct airoha_pinctrl_conf
+@@ -1543,12 +2183,73 @@ static const struct airoha_pinctrl_conf
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
int pin)
-@@ -2267,8 +2968,40 @@ static const struct airoha_pinctrl_match
+@@ -1714,7 +2415,7 @@ static const struct irq_chip airoha_gpio
+ };
+
+ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
+- struct platform_device *pdev)
++ struct platform_device *pdev)
+ {
+ struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
+ struct gpio_chip *gc = &chip->chip;
+@@ -1749,7 +2450,7 @@ static int airoha_pinctrl_add_gpiochip(s
+ return irq;
+
+ err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
+- dev_name(dev), pinctrl);
++ dev_name(dev), pinctrl);
+ if (err) {
+ dev_err(dev, "error requesting irq %d: %d\n", irq, err);
+ return err;
+@@ -1813,8 +2514,8 @@ static int airoha_pinmux_set_mux(struct
+ }
+
+ static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
+- struct pinctrl_gpio_range *range,
+- unsigned int p, bool input)
++ struct pinctrl_gpio_range *range,
++ unsigned int p, bool input)
+ {
+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 mask, index;
+@@ -1904,7 +2605,7 @@ static int airoha_pinctrl_set_conf(struc
+
+
+ if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
+- val << __ffs(reg->mask)))
++ val << __ffs(reg->mask)))
+ return -EINVAL;
+
+ return 0;
+@@ -2123,8 +2824,8 @@ static int airoha_pinconf_group_get(stru
+
+ for (i = 0; i < pinctrl->grps[group].npins; i++) {
+ if (airoha_pinconf_get(pctrl_dev,
+- pinctrl->grps[group].pins[i],
+- config))
++ pinctrl->grps[group].pins[i],
++ config))
+ return -ENOTSUPP;
+
+ if (i && cur_config != *config)
+@@ -2285,8 +2986,40 @@ static const struct airoha_pinctrl_match
},
};
projects / thirdparty / openwrt.git / commitdiff
