KVM: arm64: Calculate cptr_el2 traps on activating traps

[ Upstream commit 2fd5b4b0e7b440602455b79977bfa64dea101e6c ]

Similar to VHE, calculate the value of cptr_el2 from scratch on
activate traps. This removes the need to store cptr_el2 in every
vcpu structure. Moreover, some traps, such as whether the guest
owns the fp registers, need to be set on every vcpu run.

Reported-by: James Clark <james.clark@linaro.org>
Fixes: 5294afdbf45a ("KVM: arm64: Exclude FP ownership from kvm_vcpu_arch")
Signed-off-by: Fuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20241216105057.579031-13-tabba@google.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 757f4dea1e563657eb5c79e624e4b91f514a113a..c13a0d5907e8756cbbf458847403bab78de7947c 100644 (file)
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -330,7 +330,6 @@ struct kvm_vcpu_arch {
        /* Values of trap registers for the guest. */
        u64 hcr_el2;
        u64 mdcr_el2;
-       u64 cptr_el2;
 
        /* Values of trap registers for the host before guest entry. */
        u64 mdcr_el2_host;

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 4cf43f118d122fd6e594c25ab11fc69a9333adf7..6eb992056c67f2ca648aeeaadbcb9621125ab52a 100644 (file)
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1234,7 +1234,6 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
        }
 
        vcpu_reset_hcr(vcpu);
-       vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
 
        /*
         * Handle the "start in power-off" case.

diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 85d3b7ae720fb0ae78e79709e9c555ab01531e0d..93586bf80ec9f2bab44625253fed71654e22c87c 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -17,7 +17,6 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
        const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
        u64 hcr_set = HCR_RW;
        u64 hcr_clear = 0;
-       u64 cptr_set = 0;
 
        /* Protected KVM does not support AArch32 guests. */
        BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0),
@@ -44,16 +43,10 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
        /* Trap AMU */
        if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) {
                hcr_clear |= HCR_AMVOFFEN;
-               cptr_set |= CPTR_EL2_TAM;
        }
 
-       /* Trap SVE */
-       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids))
-               cptr_set |= CPTR_EL2_TZ;
-
        vcpu->arch.hcr_el2 |= hcr_set;
        vcpu->arch.hcr_el2 &= ~hcr_clear;
-       vcpu->arch.cptr_el2 |= cptr_set;
 }
 
 /*
@@ -83,7 +76,6 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
        const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
        u64 mdcr_set = 0;
        u64 mdcr_clear = 0;
-       u64 cptr_set = 0;
 
        /* Trap/constrain PMU */
        if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) {
@@ -110,13 +102,8 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
        if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids))
                mdcr_set |= MDCR_EL2_TTRF;
 
-       /* Trap Trace */
-       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids))
-               cptr_set |= CPTR_EL2_TTA;
-
        vcpu->arch.mdcr_el2 |= mdcr_set;
        vcpu->arch.mdcr_el2 &= ~mdcr_clear;
-       vcpu->arch.cptr_el2 |= cptr_set;
 }
 
 /*
@@ -167,8 +154,6 @@ static void pvm_init_trap_regs(struct kvm_vcpu *vcpu)
        /* Clear res0 and set res1 bits to trap potential new features. */
        vcpu->arch.hcr_el2 &= ~(HCR_RES0);
        vcpu->arch.mdcr_el2 &= ~(MDCR_EL2_RES0);
-       vcpu->arch.cptr_el2 |= CPTR_NVHE_EL2_RES1;
-       vcpu->arch.cptr_el2 &= ~(CPTR_NVHE_EL2_RES0);
 }
 
 /*

diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
index 844c466f1b1f26620582972038ac2bd81f876182..58171926f9ba23844997ff02406518a312eb8bb7 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/switch.c
+++ b/arch/arm64/kvm/hyp/nvhe/switch.c
@@ -36,23 +36,39 @@ DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
 
 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
 
-static void __activate_traps(struct kvm_vcpu *vcpu)
+static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
 {
-       u64 val;
+       u64 val = CPTR_EL2_TAM; /* Same bit irrespective of E2H */
 
-       ___activate_traps(vcpu);
-       __activate_traps_common(vcpu);
+       /* !hVHE case upstream */
+       if (1) {
+               val |= CPTR_EL2_TTA | CPTR_NVHE_EL2_RES1;
 
-       val = vcpu->arch.cptr_el2;
-       val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
-       if (!guest_owns_fp_regs(vcpu)) {
-               val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
-               __activate_traps_fpsimd32(vcpu);
-       }
-       if (cpus_have_final_cap(ARM64_SME))
+               /*
+                * Always trap SME since it's not supported in KVM.
+                * TSM is RES1 if SME isn't implemented.
+                */
                val |= CPTR_EL2_TSM;
 
+               if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs(vcpu))
+                       val |= CPTR_EL2_TZ;
+
+               if (!guest_owns_fp_regs(vcpu))
+                       val |= CPTR_EL2_TFP;
+       }
+
+       if (!guest_owns_fp_regs(vcpu))
+               __activate_traps_fpsimd32(vcpu);
+
        write_sysreg(val, cptr_el2);
+}
+
+static void __activate_traps(struct kvm_vcpu *vcpu)
+{
+       ___activate_traps(vcpu);
+       __activate_traps_common(vcpu);
+       __activate_cptr_traps(vcpu);
+
        write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
 
        if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {