arm: [MVE intrinsics] factorize vsriq

Factorize vsriq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (mve_insn): Add vsri.
	* config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_n_<supf><mode>): .,. this.
	(mve_vsriq_m_n_<supf><mode>): Rename into ...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 7e7219033cf305bed594fa49b77cc1b21df8c760..597c1dae640c93bf80e3882db56832f12b9e85e8 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1183,6 +1183,8 @@
                 (VSHRQ_N_S "vshr") (VSHRQ_N_U "vshr")
                 (VSLIQ_M_N_S "vsli") (VSLIQ_M_N_U "vsli")
                 (VSLIQ_N_S "vsli") (VSLIQ_N_U "vsli")
+                (VSRIQ_M_N_S "vsri") (VSRIQ_M_N_U "vsri")
+                (VSRIQ_N_S "vsri") (VSRIQ_N_U "vsri")
                 (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
                 (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
                 (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index a1c2cad9d2ed12246d0310a856d7ea9691f81d80..85d701a66b3a5c29a9c9e4a018d64f6d2cb61ac0 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2074,7 +2074,7 @@
 ;;
 ;; [vsriq_n_u, vsriq_n_s])
 ;;
-(define_insn "mve_vsriq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2083,7 +2083,7 @@
         VSRIQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vsri.%#<V_sz_elem>\t%q0, %q2, %3"
+  "<mve_insn>.%#<V_sz_elem>\t%q0, %q2, %3"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2641,7 +2641,7 @@
 ;;
 ;; [vsriq_m_n_s, vsriq_m_n_u])
 ;;
-(define_insn "mve_vsriq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2651,7 +2651,7 @@
         VSRIQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3"
+  "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
   [(set_attr "type" "mve_move")
    (set_attr "length" "8")])