* For devices with more than one control interface, we assume the
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
-@@ -2358,6 +2358,8 @@ static const struct usb_audio_quirk_flag
+@@ -2360,6 +2360,8 @@ static const struct usb_audio_quirk_flag
QUIRK_FLAG_ALIGN_TRANSFER),
DEVICE_FLG(0x534d, 0x2109, /* MacroSilicon MS2109 */
QUIRK_FLAG_ALIGN_TRANSFER),
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -4804,11 +4804,7 @@ static void r8169_phylink_handler(struct
+@@ -4813,11 +4813,7 @@ static void r8169_phylink_handler(struct
if (netif_carrier_ok(ndev)) {
rtl_link_chg_patch(tp);
pm_request_resume(d);
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -5517,11 +5517,6 @@ static int rtl_init_one(struct pci_dev *
+@@ -5526,11 +5526,6 @@ static int rtl_init_one(struct pci_dev *
dev->features |= dev->hw_features;
if (rtl_chip_supports_csum_v2(tp)) {
dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
-@@ -5532,6 +5527,17 @@ static int rtl_init_one(struct pci_dev *
+@@ -5541,6 +5536,17 @@ static int rtl_init_one(struct pci_dev *
netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
}
};
static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
-@@ -3920,6 +3999,9 @@ static void rtl_hw_start_8125(struct rtl
+@@ -3929,6 +4008,9 @@ static void rtl_hw_start_8125(struct rtl
break;
}
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -4827,10 +4827,8 @@ static void rtl_task(struct work_struct
+@@ -4836,10 +4836,8 @@ static void rtl_task(struct work_struct
container_of(work, struct rtl8169_private, wk.work);
int ret;
if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
/* if chip isn't accessible, reset bus to revive it */
-@@ -4839,7 +4837,7 @@ static void rtl_task(struct work_struct
+@@ -4848,7 +4846,7 @@ static void rtl_task(struct work_struct
if (ret < 0) {
netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
netif_device_detach(tp->dev);
}
}
-@@ -4858,8 +4856,6 @@ reset:
+@@ -4867,8 +4865,6 @@ reset:
} else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
rtl_reset_work(tp);
}
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -617,7 +617,6 @@ struct rtl8169_tc_offsets {
+@@ -619,7 +619,6 @@ struct rtl8169_tc_offsets {
};
enum rtl_flag {
RTL_FLAG_TASK_RESET_PENDING,
RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
RTL_FLAG_TASK_TX_TIMEOUT,
-@@ -2502,11 +2501,9 @@ u16 rtl8168h_2_get_adc_bias_ioffset(stru
+@@ -2505,11 +2504,9 @@ u16 rtl8168h_2_get_adc_bias_ioffset(stru
static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
{
}
static void rtl8169_init_phy(struct rtl8169_private *tp)
-@@ -4827,9 +4824,6 @@ static void rtl_task(struct work_struct
+@@ -4836,9 +4833,6 @@ static void rtl_task(struct work_struct
container_of(work, struct rtl8169_private, wk.work);
int ret;
if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
/* if chip isn't accessible, reset bus to revive it */
if (RTL_R32(tp, TxConfig) == ~0) {
-@@ -4913,6 +4907,7 @@ static int r8169_phy_connect(struct rtl8
+@@ -4922,6 +4916,7 @@ static int r8169_phy_connect(struct rtl8
static void rtl8169_down(struct rtl8169_private *tp)
{
/* Clear all task flags */
bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
-@@ -4941,7 +4936,7 @@ static void rtl8169_up(struct rtl8169_pr
+@@ -4950,7 +4945,7 @@ static void rtl8169_up(struct rtl8169_pr
phy_resume(tp->phydev);
rtl8169_init_phy(tp);
napi_enable(&tp->napi);
rtl_reset_work(tp);
phy_start(tp->phydev);
-@@ -4958,8 +4953,6 @@ static int rtl8169_close(struct net_devi
+@@ -4967,8 +4962,6 @@ static int rtl8169_close(struct net_devi
rtl8169_down(tp);
rtl8169_rx_clear(tp);
free_irq(tp->irq, tp);
phy_disconnect(tp->phydev);
-@@ -5192,7 +5185,7 @@ static void rtl_remove_one(struct pci_de
+@@ -5201,7 +5194,7 @@ static void rtl_remove_one(struct pci_de
if (pci_dev_run_wake(pdev))
pm_runtime_get_noresume(&pdev->dev);
if (IS_ENABLED(CONFIG_R8169_LEDS))
r8169_remove_leds(tp->leds);
-@@ -5570,6 +5563,7 @@ static int rtl_init_one(struct pci_dev *
+@@ -5579,6 +5572,7 @@ static int rtl_init_one(struct pci_dev *
tp->irq = pci_irq_vector(pdev, 0);
INIT_WORK(&tp->wk.work, rtl_task);
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -1345,40 +1345,19 @@ static void rtl8168ep_stop_cmac(struct r
+@@ -1348,40 +1348,19 @@ static void rtl8168ep_stop_cmac(struct r
RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
}
}
static void rtl8168_driver_start(struct rtl8169_private *tp)
-@@ -1392,7 +1371,8 @@ static void rtl8168_driver_start(struct
+@@ -1395,7 +1374,8 @@ static void rtl8168_driver_start(struct
static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
{
r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
}
static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
-@@ -1400,7 +1380,8 @@ static void rtl8168ep_driver_stop(struct
+@@ -1403,7 +1383,8 @@ static void rtl8168ep_driver_stop(struct
rtl8168ep_stop_cmac(tp);
r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
+++ /dev/null
-From f75d1fbe7809bc5ed134204b920fd9e2fc5db1df Mon Sep 17 00:00:00 2001
-From: Heiner Kallweit <hkallweit1@gmail.com>
-Date: Thu, 24 Oct 2024 22:42:33 +0200
-Subject: [PATCH] r8169: add support for RTL8125D
-
-This adds support for new chip version RTL8125D, which can be found on
-boards like Gigabyte X870E AORUS ELITE WIFI7. Firmware rtl8125d-1.fw
-for this chip version is available in linux-firmware already.
-
-Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
-Reviewed-by: Simon Horman <horms@kernel.org>
-Link: https://patch.msgid.link/d0306912-e88e-4c25-8b5d-545ae8834c0c@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/realtek/r8169.h | 1 +
- drivers/net/ethernet/realtek/r8169_main.c | 23 +++++++++++++------
- .../net/ethernet/realtek/r8169_phy_config.c | 10 ++++++++
- 3 files changed, 27 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/realtek/r8169.h
-+++ b/drivers/net/ethernet/realtek/r8169.h
-@@ -68,6 +68,7 @@ enum mac_version {
- /* support for RTL_GIGA_MAC_VER_60 has been removed */
- RTL_GIGA_MAC_VER_61,
- RTL_GIGA_MAC_VER_63,
-+ RTL_GIGA_MAC_VER_64,
- RTL_GIGA_MAC_VER_65,
- RTL_GIGA_MAC_VER_66,
- RTL_GIGA_MAC_NONE
---- a/drivers/net/ethernet/realtek/r8169_main.c
-+++ b/drivers/net/ethernet/realtek/r8169_main.c
-@@ -55,6 +55,7 @@
- #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
- #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
- #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
-+#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
- #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
- #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
-
-@@ -138,6 +139,7 @@ static const struct {
- [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
- /* reserve 62 for CFG_METHOD_4 in the vendor driver */
- [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
-+ [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1},
- [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2},
- [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3},
- };
-@@ -706,6 +708,7 @@ MODULE_FIRMWARE(FIRMWARE_8168FP_3);
- MODULE_FIRMWARE(FIRMWARE_8107E_2);
- MODULE_FIRMWARE(FIRMWARE_8125A_3);
- MODULE_FIRMWARE(FIRMWARE_8125B_2);
-+MODULE_FIRMWARE(FIRMWARE_8125D_1);
- MODULE_FIRMWARE(FIRMWARE_8126A_2);
- MODULE_FIRMWARE(FIRMWARE_8126A_3);
-
-@@ -2078,10 +2081,7 @@ static void rtl_set_eee_txidle_timer(str
- tp->tx_lpi_timer = timer_val;
- r8168_mac_ocp_write(tp, 0xe048, timer_val);
- break;
-- case RTL_GIGA_MAC_VER_61:
-- case RTL_GIGA_MAC_VER_63:
-- case RTL_GIGA_MAC_VER_65:
-- case RTL_GIGA_MAC_VER_66:
-+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
- tp->tx_lpi_timer = timer_val;
- RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
- break;
-@@ -2292,6 +2292,9 @@ static enum mac_version rtl8169_get_mac_
- { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 },
- { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
-
-+ /* 8125D family. */
-+ { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 },
-+
- /* 8125B family. */
- { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
-
-@@ -2557,9 +2560,7 @@ static void rtl_init_rxcfg(struct rtl816
- case RTL_GIGA_MAC_VER_61:
- RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
- break;
-- case RTL_GIGA_MAC_VER_63:
-- case RTL_GIGA_MAC_VER_65:
-- case RTL_GIGA_MAC_VER_66:
-+ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:
- RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
- RX_PAUSE_SLOT_ON);
- break;
-@@ -3897,6 +3898,12 @@ static void rtl_hw_start_8125b(struct rt
- rtl_hw_start_8125_common(tp);
- }
-
-+static void rtl_hw_start_8125d(struct rtl8169_private *tp)
-+{
-+ rtl_set_def_aspm_entry_latency(tp);
-+ rtl_hw_start_8125_common(tp);
-+}
-+
- static void rtl_hw_start_8126a(struct rtl8169_private *tp)
- {
- rtl_disable_zrxdc_timeout(tp);
-@@ -3946,6 +3953,7 @@ static void rtl_hw_config(struct rtl8169
- [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
- [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
- [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
-+ [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
- [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
- [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,
- };
-@@ -3963,6 +3971,7 @@ static void rtl_hw_start_8125(struct rtl
- /* disable interrupt coalescing */
- switch (tp->mac_version) {
- case RTL_GIGA_MAC_VER_61:
-+ case RTL_GIGA_MAC_VER_64:
- for (i = 0xa00; i < 0xb00; i += 4)
- RTL_W32(tp, i, 0);
- break;
---- a/drivers/net/ethernet/realtek/r8169_phy_config.c
-+++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
-@@ -1103,6 +1103,15 @@ static void rtl8125b_hw_phy_config(struc
- rtl8125b_config_eee_phy(phydev);
- }
-
-+static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
-+ struct phy_device *phydev)
-+{
-+ r8169_apply_firmware(tp);
-+ rtl8125_legacy_force_mode(phydev);
-+ rtl8168g_disable_aldps(phydev);
-+ rtl8125b_config_eee_phy(phydev);
-+}
-+
- static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
- struct phy_device *phydev)
- {
-@@ -1159,6 +1168,7 @@ void r8169_hw_phy_config(struct rtl8169_
- [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
- [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
- [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
-+ [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
- [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
- [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,
- };
#define RTL_GENERIC_PHYID 0x001cc800
#define RTL_8211FVD_PHYID 0x001cc878
-@@ -660,9 +663,18 @@ static int rtl8366rb_config_init(struct
+@@ -661,9 +664,18 @@ static int rtl8366rb_config_init(struct
}
/* get actual speed to cover the downshift case */
case 0x0000:
phydev->speed = SPEED_10;
break;
-@@ -684,6 +696,19 @@ static void rtlgen_decode_speed(struct p
+@@ -685,6 +697,19 @@ static void rtlgen_decode_speed(struct p
default:
break;
}
}
static int rtlgen_read_status(struct phy_device *phydev)
-@@ -701,7 +726,7 @@ static int rtlgen_read_status(struct phy
+@@ -702,7 +727,7 @@ static int rtlgen_read_status(struct phy
if (val < 0)
return val;
return 0;
}
-@@ -1007,11 +1032,11 @@ static int rtl822x_c45_read_status(struc
+@@ -1008,11 +1033,11 @@ static int rtl822x_c45_read_status(struc
return 0;
/* Read actual speed from vendor register. */
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -949,17 +949,25 @@ static void rtl822xb_update_interface(st
+@@ -950,17 +950,25 @@ static void rtl822xb_update_interface(st
static int rtl822x_read_status(struct phy_device *phydev)
{
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -1026,6 +1026,10 @@ static int rtl822x_c45_read_status(struc
+@@ -1027,6 +1027,10 @@ static int rtl822x_c45_read_status(struc
if (ret < 0)
return ret;
+++ /dev/null
-From f87a17ed3b51fba4dfdd8f8b643b5423a85fc551 Mon Sep 17 00:00:00 2001
-From: Heiner Kallweit <hkallweit1@gmail.com>
-Date: Tue, 15 Oct 2024 07:47:14 +0200
-Subject: [PATCH] net: phy: realtek: merge the drivers for internal NBase-T
- PHY's
-
-The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's
-which are register-compatible, at least for the registers we use here.
-So let's use just one PHY driver to support all of them.
-These internal PHY's exist also as external C45 PHY's, but on the
-internal PHY's no access to MMD registers is possible. This can be
-used to differentiate between the internal and external version.
-
-As a side effect the drivers for two now external-only drivers don't
-require read_mmd/write_mmd hooks any longer.
-
-Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
-Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/phy/realtek.c | 53 +++++++++++++++++++++++++++++++--------
- 1 file changed, 43 insertions(+), 10 deletions(-)
-
---- a/drivers/net/phy/realtek.c
-+++ b/drivers/net/phy/realtek.c
-@@ -95,6 +95,7 @@
-
- #define RTL_GENERIC_PHYID 0x001cc800
- #define RTL_8211FVD_PHYID 0x001cc878
-+#define RTL_8221B 0x001cc840
- #define RTL_8221B_VB_CG 0x001cc849
- #define RTL_8221B_VN_CG 0x001cc84a
- #define RTL_8251B 0x001cc862
-@@ -1077,6 +1078,23 @@ static bool rtlgen_supports_2_5gbps(stru
- return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
- }
-
-+/* On internal PHY's MMD reads over C22 always return 0.
-+ * Check a MMD register which is known to be non-zero.
-+ */
-+static bool rtlgen_supports_mmd(struct phy_device *phydev)
-+{
-+ int val;
-+
-+ phy_lock_mdio_bus(phydev);
-+ __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
-+ __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
-+ __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
-+ val = __phy_read(phydev, MII_MMD_DATA);
-+ phy_unlock_mdio_bus(phydev);
-+
-+ return val > 0;
-+}
-+
- static int rtlgen_match_phy_device(struct phy_device *phydev)
- {
- return phydev->phy_id == RTL_GENERIC_PHYID &&
-@@ -1086,7 +1104,8 @@ static int rtlgen_match_phy_device(struc
- static int rtl8226_match_phy_device(struct phy_device *phydev)
- {
- return phydev->phy_id == RTL_GENERIC_PHYID &&
-- rtlgen_supports_2_5gbps(phydev);
-+ rtlgen_supports_2_5gbps(phydev) &&
-+ rtlgen_supports_mmd(phydev);
- }
-
- static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
-@@ -1098,6 +1117,11 @@ static int rtlgen_is_c45_match(struct ph
- return !is_c45 && (id == phydev->phy_id);
- }
-
-+static int rtl8221b_match_phy_device(struct phy_device *phydev)
-+{
-+ return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
-+}
-+
- static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
- {
- return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
-@@ -1118,9 +1142,21 @@ static int rtl8221b_vn_cg_c45_match_phy_
- return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
- }
-
--static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
-+static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
- {
-- return rtlgen_is_c45_match(phydev, RTL_8251B, false);
-+ if (phydev->is_c45)
-+ return false;
-+
-+ switch (phydev->phy_id) {
-+ case RTL_GENERIC_PHYID:
-+ case RTL_8221B:
-+ case RTL_8251B:
-+ break;
-+ default:
-+ return false;
-+ }
-+
-+ return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
- }
-
- static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
-@@ -1382,10 +1418,8 @@ static struct phy_driver realtek_drvs[]
- .resume = rtlgen_resume,
- .read_page = rtl821x_read_page,
- .write_page = rtl821x_write_page,
-- .read_mmd = rtl822x_read_mmd,
-- .write_mmd = rtl822x_write_mmd,
- }, {
-- PHY_ID_MATCH_EXACT(0x001cc840),
-+ .match_phy_device = rtl8221b_match_phy_device,
- .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
- .get_features = rtl822x_get_features,
- .config_aneg = rtl822x_config_aneg,
-@@ -1396,8 +1430,6 @@ static struct phy_driver realtek_drvs[]
- .resume = rtlgen_resume,
- .read_page = rtl821x_read_page,
- .write_page = rtl821x_write_page,
-- .read_mmd = rtl822x_read_mmd,
-- .write_mmd = rtl822x_write_mmd,
- }, {
- PHY_ID_MATCH_EXACT(0x001cc838),
- .name = "RTL8226-CG 2.5Gbps PHY",
-@@ -1475,8 +1507,9 @@ static struct phy_driver realtek_drvs[]
- .read_page = rtl821x_read_page,
- .write_page = rtl821x_write_page,
- }, {
-- .match_phy_device = rtl8251b_c22_match_phy_device,
-- .name = "RTL8126A-internal 5Gbps PHY",
-+ .match_phy_device = rtl_internal_nbaset_match_phy_device,
-+ .name = "Realtek Internal NBASE-T PHY",
-+ .flags = PHY_IS_INTERNAL,
- .get_features = rtl822x_get_features,
- .config_aneg = rtl822x_config_aneg,
- .read_status = rtl822x_read_status,
+++ /dev/null
-From 8989bad541133c43550bff2b80edbe37b8fb9659 Mon Sep 17 00:00:00 2001
-From: Heiner Kallweit <hkallweit1@gmail.com>
-Date: Thu, 17 Oct 2024 18:01:13 +0200
-Subject: [PATCH] net: phy: realtek: add RTL8125D-internal PHY
-
-The first boards show up with Realtek's RTL8125D. This MAC/PHY chip
-comes with an integrated 2.5Gbps PHY with ID 0x001cc841. It's not
-clear yet whether there's an external version of this PHY and how
-Realtek calls it, therefore use the numeric id for now.
-
-Link: https://lore.kernel.org/netdev/2ada65e1-5dfa-456c-9334-2bc51272e9da@gmail.com/T/
-Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
-Message-ID: <7d2924de-053b-44d2-a479-870dc3878170@gmail.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Andrew Lunn <andrew@lunn.ch>
----
- drivers/net/phy/realtek.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/net/phy/realtek.c
-+++ b/drivers/net/phy/realtek.c
-@@ -1151,6 +1151,7 @@ static int rtl_internal_nbaset_match_phy
- case RTL_GENERIC_PHYID:
- case RTL_8221B:
- case RTL_8251B:
-+ case 0x001cc841:
- break;
- default:
- return false;
-LINUX_VERSION-6.12 = .35
-LINUX_KERNEL_HASH-6.12.35 = 05f4e0b01dde578c3328eb539d305cccec7b84e939f6dd5f21fdaf5f313da748
+LINUX_VERSION-6.12 = .36
+LINUX_KERNEL_HASH-6.12.36 = 4a168aed2de5a81aadd90ba2b153860a98d99bfc34651936e17f18e54f01ba8c
if (sk_can_gso(sk)) {
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
-@@ -2012,7 +2012,7 @@ void ieee80211_color_collision_detection
+@@ -2021,7 +2021,7 @@ void ieee80211_color_collision_detection
/* interface handling */
#define MAC80211_SUPPORTED_FEATURES_TX (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | \
NETIF_F_HW_CSUM | NETIF_F_SG | \
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
-@@ -74,7 +74,7 @@ enum imx_pcie_variants {
+@@ -76,7 +76,7 @@ enum imx_pcie_variants {
};
#define IMX_PCIE_FLAG_IMX_PHY BIT(0)
#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
-@@ -847,6 +847,12 @@ static int imx_pcie_start_link(struct dw
+@@ -862,6 +862,12 @@ static int imx_pcie_start_link(struct dw
u32 tmp;
int ret;
/*
* Force Gen1 operation when starting the link. In case the link is
* started in Gen2 mode, there is a possibility the devices on the
-@@ -883,22 +889,10 @@ static int imx_pcie_start_link(struct dw
+@@ -898,22 +904,10 @@ static int imx_pcie_start_link(struct dw
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
dw_pcie_dbi_ro_wr_dis(pci);
}
/* Make sure link training is finished as well! */
-@@ -1520,7 +1514,7 @@ static const struct imx_pcie_drvdata drv
+@@ -1535,7 +1529,7 @@ static const struct imx_pcie_drvdata drv
[IMX6Q] = {
.variant = IMX6Q,
.flags = IMX_PCIE_FLAG_IMX_PHY |
IMX_PCIE_FLAG_BROKEN_SUSPEND |
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.dbi_length = 0x200,
-@@ -1538,7 +1532,7 @@ static const struct imx_pcie_drvdata drv
+@@ -1553,7 +1547,7 @@ static const struct imx_pcie_drvdata drv
[IMX6SX] = {
.variant = IMX6SX,
.flags = IMX_PCIE_FLAG_IMX_PHY |
IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6sx_clks,
-@@ -1554,7 +1548,7 @@ static const struct imx_pcie_drvdata drv
+@@ -1569,7 +1563,7 @@ static const struct imx_pcie_drvdata drv
[IMX6QP] = {
.variant = IMX6QP,
.flags = IMX_PCIE_FLAG_IMX_PHY |
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
-@@ -763,7 +763,6 @@ static int imx7d_pcie_core_reset(struct
+@@ -778,7 +778,6 @@ static int imx7d_pcie_core_reset(struct
static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
reset_control_assert(imx_pcie->pciephy_reset);
if (imx_pcie->drvdata->core_reset)
imx_pcie->drvdata->core_reset(imx_pcie, true);
-@@ -775,7 +774,6 @@ static void imx_pcie_assert_core_reset(s
+@@ -790,7 +789,6 @@ static void imx_pcie_assert_core_reset(s
static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
reset_control_deassert(imx_pcie->pciephy_reset);
if (imx_pcie->drvdata->core_reset)
imx_pcie->drvdata->core_reset(imx_pcie, false);
-@@ -976,6 +974,9 @@ static int imx_pcie_host_init(struct dw_
+@@ -991,6 +989,9 @@ static int imx_pcie_host_init(struct dw_
}
}
if (priv->dma_cap.host_dma_width <= 32)
gfp |= GFP_DMA32;
-@@ -4792,7 +4792,7 @@ static inline void stmmac_rx_refill(stru
+@@ -4789,7 +4789,7 @@ static inline void stmmac_rx_refill(stru
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
int dirty = stmmac_rx_dirty(priv, queue);
unsigned int entry = rx_q->dirty_rx;
projects / thirdparty / openwrt.git / commitdiff
