pinctrl: aspeed: Fix GPIO mux value for ADC-capable balls

aspeed_g7_soc1_gpio_request_enable() unconditionally writes mux
function 0 to route the requested pin to GPIO. This is wrong for the
ADC-capable balls W17 through AB19 (ADC0-ADC15), where function 0
selects the ADC input and function 1 selects GPIO. Requesting one of
those GPIOs therefore muxed the ball to ADC instead.

Write mux value 1 for balls W17 through AB19 so the GPIO function is
actually selected.

Fixes: 4af4eb66aac3 ("pinctrl: aspeed: Add AST2700 SoC1 support")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
index a1ef52ad5c752a33f30a2fdee08aded8c7b2579c..50027d69c34286a436d6c8aa29663cdc3a6d2598 100644 (file)
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
@@ -691,12 +691,21 @@ static int aspeed_g7_soc1_gpio_request_enable(struct pinctrl_dev *pctldev,
 {
        struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
        struct aspeed_g7_field field;
+       unsigned int val = 0;
        int ret = -ENOTSUPP;
 
        if (pin <= AC24) {
+               /*
+                * Balls W17 through AB19 are the ADC-capable pins: mux
+                * function 0 selects the ADC input and function 1 selects
+                * GPIO, unlike all other pins where function 0 is GPIO.
+                */
+               if (pin >= W17 && pin <= AB19)
+                       val = 1;
                field = aspeed_g7_soc1_pinmux_field_from_pin(pin);
                ret = regmap_update_bits(pctl->regmap, field.reg,
-                                        field.mask << field.shift, 0);
+                                        field.mask << field.shift,
+                                        val << field.shift);
        }
 
        return ret;