arm64: enable support for: str bN, [reg, reg etc]

and str hN, [reg, reg etc].  Fixes #337762.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2943

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 735373e4223c02b598c8ae0a264a7e9fac186db1..27d7b4cb480e027425352a0236af86d4e79a39b7 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -4399,7 +4399,6 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
                putQRegLO(tt, loadLE(Ity_I8, mkexpr(ea)));
                DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I8), dis_buf);
             } else {
-               vassert(0); //ATC
                storeLE(mkexpr(ea), getQRegLO(tt, Ity_I8));
                DIP("str %s, %s\n", nameQRegLO(tt, Ity_I8), dis_buf);
             }
@@ -4410,7 +4409,6 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
                putQRegLO(tt, loadLE(Ity_I16, mkexpr(ea)));
                DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I16), dis_buf);
             } else {
-               vassert(0); //ATC
                storeLE(mkexpr(ea), getQRegLO(tt, Ity_I16));
                DIP("str %s, %s\n", nameQRegLO(tt, Ity_I16), dis_buf);
             }