drm/amd/display: Refactor DML2 DC power instance

[WHY & HOW]
Use a dedicated DC power option and instance pair.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 13334ee987f7a84dde5d7bb1874b22dc703f0e8d..514a5efda1021607ec3f3a1ccf8026424be70549 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -311,6 +311,25 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
        dcn401_build_wm_range_table(clk_mgr_base);
 }
 
+bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base)
+{
+       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+       return clk_mgr->smu_present && clk_mgr->dpm_present &&
+                       ((clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz) ||
+                       (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz) ||
+                       (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz) ||
+                       (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz) ||
+                       (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz) ||
+                       (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels &&
+                       clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz));
+}
+
 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
                struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 {
@@ -1496,6 +1515,7 @@ static struct clk_mgr_funcs dcn401_funcs = {
                .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
                .get_hard_min_memclk = dcn401_get_hard_min_memclk,
                .get_hard_min_fclk = dcn401_get_hard_min_fclk,
+               .is_dc_mode_present = dcn401_is_dc_mode_present,
 };
 
 struct clk_mgr_internal *dcn401_clk_mgr_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
index 6c9ae5ca2c7e96975e384d3b76799ffd65c839d4..616e964df96df07b4e19fdf3af29d26fa08954fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -105,6 +105,7 @@ struct dcn401_clk_mgr {
 };
 
 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
+bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
 
 struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,
                struct dccg *dccg);

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 4db7383720fd0853e340e06f52994f843e326b73..47712a4aec55ba89e325378af19bd875f284e001 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -194,11 +194,6 @@ static void init_state(struct dc *dc, struct dc_state *state)
 struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)
 {
        struct dc_state *state;
-#ifdef CONFIG_DRM_AMD_DC_FP
-       struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
-
-       memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
-#endif
 
        state = kvzalloc(sizeof(struct dc_state), GFP_KERNEL);
 
@@ -211,14 +206,12 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p
 
 #ifdef CONFIG_DRM_AMD_DC_FP
        if (dc->debug.using_dml2) {
-               dml2_opt->use_clock_dc_limits = false;
-               if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2)) {
+               if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) {
                        dc_state_release(state);
                        return NULL;
                }
 
-               dml2_opt->use_clock_dc_limits = true;
-               if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source)) {
+               if (!dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) {
                        dc_state_release(state);
                        return NULL;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 83ee6ddaddb74efce3938c9b8a01798c4ef569bc..fc36beb66d49f3aee4406da8a4e2cbd74d98f309 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1701,7 +1701,7 @@ struct dc {
        } scratch;
 
        struct dml2_configuration_options dml2_options;
-       struct dml2_configuration_options dml2_tmp;
+       struct dml2_configuration_options dml2_dc_power_options;
        enum dc_acpi_cm_power_state power_state;
 
 };

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 97c3482721db68a4a32c2a24e2d2b08167a248b6..ffc5f0e600bd7f65000de5f14bf21b8d10296ce8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -145,13 +145,8 @@ void dcn401_init_hw(struct dc *dc)
                dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 
                // mark dcmode limits present if any clock has distinct AC and DC values from SMU
-               dc->caps.dcmode_power_limits_present =
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dcfclk_mhz) ||
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dispclk_mhz) ||
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dtbclk_mhz) ||
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.fclk_mhz) ||
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.memclk_mhz) ||
-                               (dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.socclk_mhz);
+               dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&
+                               dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);
        }
 
        // Initialize the dccg

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index c14d64687a3d421a84060a19fc74db50ffe3c20a..3b736f4687a683ddf3bcddb75bb173590f350271 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -324,6 +324,8 @@ struct clk_mgr_funcs {
 
        int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);
 
+       bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr);
+
 };
 
 struct clk_mgr {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index a7a78a2752de2697dd1c833cc739f3c7125a8ea6..363e4a094534d44dd1fc7b7ca05928fd3008490e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2061,21 +2061,15 @@ void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
 
 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
-       struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
-
-       memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
-
        DC_FP_START();
 
        dcn32_update_bw_bounding_box_fpu(dc, bw_params);
 
-       dml2_opt->use_clock_dc_limits = false;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
+               dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
 
-       dml2_opt->use_clock_dc_limits = true;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
+               dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
 
        DC_FP_END();
 }
@@ -2551,6 +2545,10 @@ static bool dcn32_resource_construct(
        if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
                dc->config.sdpif_request_limit_words_per_umc = 16;
 
+       /* init DC limited DML2 options */
+       memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
+       dc->dml2_dc_power_options.use_clock_dc_limits = true;
+
        return true;
 
 create_fail:

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 7db1f7a5613fe02749d6377a5381422f146c57b6..ae5a58a48d73ee958ecf620ca821664c4475d1f9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1580,21 +1580,15 @@ static struct dc_cap_funcs cap_funcs = {
 
 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
-       struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
-
-       memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
-
        DC_FP_START();
 
        dcn321_update_bw_bounding_box_fpu(dc, bw_params);
 
-       dml2_opt->use_clock_dc_limits = false;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
+               dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
 
-       dml2_opt->use_clock_dc_limits = true;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
+               dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
 
        DC_FP_END();
 }
@@ -2046,6 +2040,10 @@ static bool dcn321_resource_construct(
        dc->dml2_options.max_segments_per_hubp = 18;
        dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
 
+       /* init DC limited DML2 options */
+       memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
+       dc->dml2_dc_power_options.use_clock_dc_limits = true;
+
        return true;
 
 create_fail:

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index aff30274fa969c07d6416f8147ae54e60afd4be5..b0cf5c9c1cad60ca74661c6d56786ccd2c07cb67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1607,10 +1607,6 @@ static struct dc_cap_funcs cap_funcs = {
 
 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
-       struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
-
-       memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
-
        /* re-calculate the available MALL size if required */
        if (bw_params->num_channels > 0) {
                dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
@@ -1621,13 +1617,11 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 
        DC_FP_START();
 
-       dml2_opt->use_clock_dc_limits = false;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
+               dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
 
-       dml2_opt->use_clock_dc_limits = true;
        if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
-               dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
+               dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
 
        DC_FP_END();
 }
@@ -2246,6 +2240,10 @@ static bool dcn401_resource_construct(
        /* SPL */
        dc->caps.scl_caps.sharpener_support = true;
 
+       /* init DC limited DML2 options */
+       memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
+       dc->dml2_dc_power_options.use_clock_dc_limits = true;
+
        return true;
 
 create_fail: