arm64: dts: mediatek: mt7988: add spi controllers

Add SPI controllers for mt7988.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 8f6d1dfae24ac30e91207074a955d0b7c8ca2895..8c31935f4ab007e035cfb5fa2dddb14e8abd1e15 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -311,6 +311,51 @@
                        status = "disabled";
                };
 
+               spi0: spi@11007000 {
+                       compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+                       reg = <0 0x11007000 0 0x100>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPI_SEL>,
+                                <&infracfg CLK_INFRA_104M_SPI0>,
+                                <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk",
+                                     "hclk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi1: spi@11008000 {
+                       compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
+                       reg = <0 0x11008000 0 0x100>;
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPIM_MST_SEL>,
+                                <&infracfg CLK_INFRA_104M_SPI1>,
+                                <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk",
+                                     "hclk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi2: spi@11009000 {
+                       compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+                       reg = <0 0x11009000 0 0x100>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPI_SEL>,
+                                <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+                                <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk",
+                                     "hclk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                lvts: lvts@1100a000 {
                        compatible = "mediatek,mt7988-lvts-ap";
                        #thermal-sensor-cells = <1>;