clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks

The UFS symbol RX/TX mux clocks were not defined previously.
Add these mux clocks so that clock rate propagation reaches
the muxes correctly.

Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260103-ufs_symbol_clk-v2-2-51828cc76236@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index b63c8abdd2fc24fc963f038f8cdcafd7598ba989..ae9621aff85831caa7aeecce8480791deee2f9ef 100644 (file)
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -59,6 +59,9 @@ enum {
        DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
        DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
        DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+       DT_UFS_PHY_RX_SYMBOL_0_CLK,
+       DT_UFS_PHY_RX_SYMBOL_1_CLK,
+       DT_UFS_PHY_TX_SYMBOL_0_CLK,
 };
 
 enum {
@@ -103,6 +106,9 @@ enum {
        P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
        P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
        P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+       P_UFS_PHY_RX_SYMBOL_0_CLK,
+       P_UFS_PHY_RX_SYMBOL_1_CLK,
+       P_UFS_PHY_TX_SYMBOL_0_CLK,
 };
 
 static struct clk_alpha_pll gcc_gpll0 = {
@@ -482,6 +488,48 @@ static const struct clk_parent_data gcc_parent_data_33[] = {
        { .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 };
 
+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
+       .reg = 0x77064,
+       .clkr = {
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
+                       .parent_data = &(const struct clk_parent_data) {
+                               .index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_regmap_phy_mux_ops,
+               },
+       },
+};
+
+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
+       .reg = 0x770e0,
+       .clkr = {
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
+                       .parent_data = &(const struct clk_parent_data) {
+                               .index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_regmap_phy_mux_ops,
+               },
+       },
+};
+
+static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
+       .reg = 0x77054,
+       .clkr = {
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
+                       .parent_data = &(const struct clk_parent_data) {
+                               .index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_regmap_phy_mux_ops,
+               },
+       },
+};
+
 static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
        .reg = 0x9f06c,
        .clkr = {
@@ -5148,12 +5196,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
 
 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
        .halt_reg = 0x7702c,
-       .halt_check = BRANCH_HALT,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x7702c,
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data) {
                        .name = "gcc_ufs_phy_rx_symbol_0_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -5161,12 +5214,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
 
 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
        .halt_reg = 0x770cc,
-       .halt_check = BRANCH_HALT,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x770cc,
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data) {
                        .name = "gcc_ufs_phy_rx_symbol_1_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -5174,12 +5232,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
 
 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
        .halt_reg = 0x77028,
-       .halt_check = BRANCH_HALT,
+       .halt_check = BRANCH_HALT_DELAY,
        .clkr = {
                .enable_reg = 0x77028,
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data) {
                        .name = "gcc_ufs_phy_tx_symbol_0_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -7180,6 +7243,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
        [GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
        [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
        [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
+       [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
+       [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
+       [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
 };
 
 static struct gdsc *gcc_x1e80100_gdscs[] = {